Hsing-Huang Tseng

Si tunnel transistors with a novel silicided source and 46mV/dec swing

We report a novel tunneling field effect transistor (TFET) fabricated with a high-k/metal gate stack and using nickel silicide to create a special field-enhancing geometry and a high dopant density by dopant segregation. It produces steep subthreshold swing (SS) of 46mV/dec and high ION/IOFF ratio (∼108) and the experiment was successfully repeated after two months. Its superior operation is explained through simulation. For the first time convincing statistical evidence of sub-60mV/dec SS is presented. More than 30% of the devices show sub-60mV/dec SS after systemic data quality checks that screen out unreliable data.

InGaAs MOSFET performance and reliability improvement by simultaneous reduction of oxide and interface charge in ALD (La)AlOx/ZrO 2 gate stack

The performance and reliability of ZrO<inf>2</inf>/In<inf>0.53</inf>Ga<inf>0.47</inf>As MOSFETs are shown to be improved by simultaneous reduction of dielectric and interface charges. An amorphous (La)AlO<inf>x</inf> interlayer at the ZrO<inf>2</inf>/In<inf>0.53</inf>Ga<inf>0.47</inf>As interface is a key to reduce border traps, interface traps and move ZrO<inf>2</inf> fixed charge away from the In<inf>0.53</inf>Ga<inf>0.47</inf>As. Border traps are reduced ∼3x, effective fixed charges are reduced ∼3x and interface trap density is reduced ∼1.5x. The net effect of the improved stack is 50% normalized I<inf>d</inf> improvement and 75% normalized G<inf>m</inf> improvement. P/NBTI cyclic stress results indicate Al<inf>2</inf>O<inf>3</inf>/ZrO<inf>2</inf> is more reliable than ZrO<inf>2</inf> only. ΔV<inf>th</inf> of the bilayer show excellent repeatability; conversely, ΔV<inf>th</inf> of ZrO<inf>2</inf> shows permanent (not recoverable) interface degradation during relaxation (NBTI stress). La incorporation in Al<inf>2</inf>O<inf>3</inf> increases the к-value while providing improved reliability over both the ZrO<inf>2</inf> and Al<inf>2</inf>O<inf>3</inf>/ZrO<inf>2</inf> stack.

Gate-First Integration of Tunable Work Function Metal Gates of Different Thicknesses Into High-

Gate-first integration of tunable work function metal gates of different thicknesses (3-20 nm) into high-k/metal gates CMOS FinFETs was demonstrated to achieve multiple threshold voltages (VTh) for 32-nm technology and beyond logic, memory, input/output, and system-on-a-chip applications. The fabricated devices showed excellent short-channel effect immunity (drain-induced barrier lowering ~40 mV/V), nearly symmetric VTh, low Tinv (~1.4 nm), and high Ion (~780 ¿A/¿m) for N/PMOS without any intentional strain enhancement.

k

We demonstrate best in class performance for MANOS-type charge-trap flash non-volatile memory devices through improved program/erase (P/E), endurance and retention. Band-engineered (BE) tunnel-oxides (TO) and BE-SiNx charge-trap layers are employed to optimize program, erase, and endurance with trade-off in retention. However, for the 1st time we combine BE-TO, BE-SiNx, BE-blocking layer (BE-BL) and an oxygen-bearing high effective-work-function (EWF) electrode to dramatically improve retention while maintaining the combined benefits from the engineering of each individual stack component. Resulting device improvements include larger ΔVth P/E windows of ≫300%, enduring P/E cycles to at least 100K cycles while maintaining a window ≫4V, and retention approaching zero% charge loss over 24 hours at 150°C. The large, enduring windows with improved retention are favorable for multi-level cell application beyond the 30nm node.

/Metal Gates CMOS FinFETs for Multi-

Si-tunneling field effect transistors (TFETs) with a record I<inf>on</inf> >100 µA/µm and high I<inf>on</inf>/I<inf>off</inf> ratio (> 10⁵) at V<inf>ds</inf>=1V are reported. Using an optimal spike and millisec flash anneal coupled with an engineered source-gate overlap through a gate-last process, Si TFETs have been demonstrated with 10 to 1000 times greater current than previously reported. The devices exhibit negative differential resistance and temperature dependencies consistent with band-to-band tunneling and current characteristics in excellent agreement with 2D TCAD simulations.

V_{\rm Th}

High mobility, narrow band gap group IV and III-V materials are strong contenders to replace strained-Si channels for logic applications beyond the 16 nm node [1–3]. While there are many research efforts evaluating III-V channels in HEMT and MOSFET forms, model based understanding and control of the FET properties such as channel mobility, series resistance, and off-state leakage are still lacking [4–8]. In this work, we address the aforementioned issues, by investigating laser annealing to control thermal budget and lower series resistance. Additionally we also report on preliminary material analysis and demonstrate the low temperature measurement to the performance of In<inf>0.53</inf>Ga<inf>0.47</inf>As MOSFETs. The electrical and material characteristics of TaN/ZrO<inf>2</inf>/In<inf>0.53</inf>Ga<inf>0.47</inf>As self-aligned n-MOSFETs with high I<inf>on</inf>/I<inf>off</inf> (> 5×10⁴), high mobility (~ 3000 cm /V•sec) and promise for low R<inf>ext</inf> are presented and discussed.

Engineering

We present a comparative study of the effects of a Si capping layer on SiGe channel pMOSFETs used for radio-frequency (RF) applications. In Si-capped devices, the drive current increases because Si/SiGe heterojunction layers form a SiGe quantum well, which reduces carrier scattering. Conversely, SiGe samples without a Si capping layer suffer severe interface degradation, due to Ge diffusing into the gate dielectric. Devices using a Si capping layer have enhanced RF performance and reduced low-frequency noise, which is a key factor affecting phase noise. There is an increase in the RF figures of merit. These benefits indicate that a Si capping layer should be used in SiGe channel pMOSFETs.

Engineering the complete MANOS-type NVM stack for best in class retention performance

This study presents the application of X-ray metrology for phase engineering of high-k materials. In particular, grazing angle X-ray diffraction (GIXRD) is used to measure the phase and lattice constants of HfO2 doped with varying amounts of SiO2. Using the molar volume obtained from GIXRD as a guide, we narrow down the compositional range of SiO2 that exhibits a higher dielectric constant in device measurements. This scheme can be employed for screening dopants, optimizing composition, and reducing the typical development cycle from weeks to less than two hours.