Huajun Fang

Transconductance improvement method for low-voltage bulk-driven input stage

A proposed transconductance enhanced method for low-voltage bulk-driven input stage is presented in this paper. The basic idea is to use current-shunt auxiliary amplifier to improve the voltage gain from the inputs to the gates of bulk-driven pairs. The enhanced voltage gain of the auxiliary amplifier leads to the improvement of the effective transconductance of the input stage. Results show that the transconductance of the OTA using the proposed bulk-driven input stage improves almost 200% without additional power and area dissipation compared to the conventional bulk-driven counterpart. Author-HighlightsWe propose a transconductance improvement method for bulk-driven input stage.The proposed method enhances transconductance without additional power.The proposed input stage is suitable for low-voltage and low-power application.We propose a modified composite-transistor to enhance dc gain of OTA.

DC gain enhancement method for recycling folded cascode amplifier in deep submicron CMOS technology

A DC gain enhanced recycling folded cascode amplifier with a new positive feedback output stage is presented. The proposed amplifier using positive feedback to cancel the output conductance allows DC gain to be enhanced without affecting the bandwidth of the amplifier. The proposed amplifier was implemented in SMIC standard 65 nm CMOS process. Simulation results show that a DC gain enhancement of 35 dB is achieved without limiting the bandwidth.

A low power constant-Gm rail-to-rail operational transconductance amplifier by recycling current

A modification to the conventional constant-gm rail-to-rail operational transconductance amplifier is presented. The proposed amplifier has the benefit of delivering the same performance while consuming a fraction of the power compared to the conventional rail-to-rail amplifier. This is achieved by recycling the bias current of idle devices, which results in an enhanced transconductance, gain and slew rate. The proposed amplifier was implemented in SMIC standard 65nm CMOS process. Simulation results show that the proposed amplifier achieves 168.1MHz unity-gain bandwidth, 63.8dB DC gain, 23.4V/us slew rate and less than 8% deviation in transconductance, but the power consumption reduced by 50% compared to the conventional rail-to-rail amplifier with the same design specifications.

A power-efficient improved recycling folded cascode amplifier

An improved recycling folded cascode amplifier for wide-bandwidth ΣΔ modulator is presented in this article. The proposed amplifier introduces internal positive-feedback pairs to achieve a significant boost in transconductance and DC gain without increasing power or area budget. The proposed recycling folded cascode amplifier was implemented in SMIC standard 65 nm CMOS process. Compared to other recycling folded cascode structures, simulation results show that the proposed amplifier achieves the enhancement of gain-bandwidth and DC gain with the best figure-of-merits.

An ultra-low-power reconfigurable two-stage OTA with improved transconductance and DC gain

ABSTRACT An ultra-low-power reconfigurable bulk-driven two-stage operational transconductance amplifier (OTA) with enhanced transconductance and dc gain is presented in this article. By means of the partial positive-feedback technique, the effective bulk transconductance of the input stage is improved. Also, the proposed composite-transistor is used to enhance the dc gain of the OTA. In addition, a proposed pseudo-cascode compensation technique to improve the stability of the two-stage OTA in ultra-low-voltage condition, which makes the OTA reconfigurable, is introduced. Transistor-level simulations in UMC 0.18m CMOS process confirm the theoretical results. Simulated from a 0.5-V supply voltage, the proposed OTA achieves a 98 dB dc gain, a 15.5kHz gain-bandwidth and the phase margin varies less than 6% as the bias current scaled by a factor of 200. The power of the proposed OTA is only 38nW.

A new low power symmetric folded cascode amplifier by recycling current in 65nm CMOS technology

A new low power symmetric folded cascode amplifier is presented. The proposed amplifier delivers the same performance as that of the conventional symmetric folded cascode amplifier while consuming only 50% the power. This is achieved by recycling the bias current of idle devices, which results in an enhanced transconductance, gain and slew rate. The proposed amplifier was implemented in SMIC standard 65nm CMOS process. Simulation results show that the proposed amplifier achieves almost twice the bandwidth (313.4MHz versus 158.2MHz), 8.2dB DC gain enhancement (63.4dB versus 55.2dB) and better than twice the slew rate (45.6V/us versus 20.5V/us) compared to the conventional symmetric folded cascode amplifier with the same power. On the other hand, the power consumption of the proposed amplifier can reduce 50% compared to the conventional symmetric folded cascode amplifier with the same performance.

A low-noise low-voltage low-power bulk-driven amplifier with chopper stabilization technique

A bulk-driven operational transconductance amplifier (OTA), which adopts the chopper stabilization technique to attenuate the flicker noise and offset, is proposed in this paper. Operating in the subthreshold region, the chopped bulk-driven OTA has the abilities to work in low-voltage condition, thus consuming only nanowatt power. The circuit was simulated on UMC 180 nm CMOS process. Simulation results show that the proposed OTA achieves a noise floor of 400 nV/√Hz and an offset of 366 µV, with only 346 nA power consumption under 0.5 V supply voltage.

Chopping-Out-Of-band(COOB) for reducing ripple in chopper amplifiers

This paper introduces a method named Chopping-Out-Of-band (COOB), which can suppress ripple in chopper amplifiers. By choosing a suitable chopping frequency ( fchop) located in GBW < fchop < NLBW (NoLoad Bandwidth), the ripple will be suppressed rather than amplified and the effect can be improve further by an extra filter. The COOB technique was employed in instrumentation amplifiers as examples and the extra filter was designed to passive filter. These chopper amplifiers were simulated on UMC 0.18 um technology with the help of Cadence SpectreRF. Simulation results showed that the ripple was suppressed by −93.4 dB in Power Spectral Density (PSD) analysis without additional power consumption.

A low power and low 1/f noise chopper-stabilized amplifier with current recycling technology

A chopper stabilized amplifier with recycling current is presented. The proposed chopper stabilized amplifier with current recycling has the benefit of reducing power consumption, which the chopper stabilization increases. The proposed chopper stabilized amplifier was designed in UMC standard 180nm CMOS process. Simulation results show that this chopper stabilized amplifier achieves 20.1MHz GBW, 57.5nV/sqrt(Hz) input referred noise and 1.6mHz 1/f noise corner frequency. Compared with the conventional chopper stabilized amplifier, the power consumption reduced by 50%.

A LOW POWER CURRENT RECYCLING CONSTANT-gm RAIL-TO-RAIL OTA

A low power current recycling constant-gm rail-to-rail (RtR) OTA is presented. The proposed amplifier has the benefit of delivering the same performance while consuming half the power compared to the conventional RtR amplifier. This is achieved by recycling the bias current of idle devices, which results in an enhanced transconductance, gain and slew rate. The proposed amplifier was implemented in CSMC standard 0.18 um CMOS process. Simulation results show that the proposed amplifier achieves 10.2 MHz unity-gain bandwidth, 59.4 dB DC gain, 4.8 V/us slew rate and less than 8% deviation in transconductance, but the power consumption reduced by 50% compared to the conventional RtR amplifier with the same design specifications.