Huang Wuhuang

Analysis and implementation of data synchronization in time-interleaved ADCs system

Time-interleaved parallel technology is still the best way to implement a data acquisition system with higher sampling rate. In order to make a system of multiple analog to digital converters (ADCs) achieve an optimal performance, a large number of calibration works should be done on the parameters, such as gain, offset and time error, based on sampled data after ADCs. And it also should get correctly data sequence to store the sampled data and then to do correspondingly post-processing. However, along with the increase of sampling rate, a random reset operation of multiple ADCs system will lead to the uncertainty of data synchronous transmission and the incorrect of sampled data sequence that caused its incorrect digital post-processing. Based on an example of dual-ADC time-interleaved parallel sampling system, this paper analyzes the basic timing of sample data transmission process, and presents a calibration method of data synchronous recognition. And the guiding principles of practical engineering design are also proposed. Finally, these are tested on 20GSa/s high-speed acquisition system composed of four 5GSa/s ADCs. The results indicate that the calibration method of data synchronization and the guiding principles of practical engineering design are effective and reliable, and provide a strong support for structure of more complex high-speed time-interleaved ADCs system.

Design and implementation of 500GSPS random equivalent sampling

With the increase in horizontal scanning speed, the time observing window narrows down, so the high random equivalent sampling rate is needed. There are two key points that determine equivalent sampling rate, namely real-time sampling rate of analog-digital converter and high resolution of time interval measurement. In this paper, a method of multichannel random equivalent sampling based on time-interleaved ADC structure is proposed. the crucial time-interval measurement circuit based on time to Amplitude was introduced and explored. Besides, a high-speed trigger channel is needed for high speed data acquire, the relationship of trigger signal and data synchronized clock was discussed, and the circuit of trigger channel was gave. The experimental data show that 500GSPS random equivalent sampling rate was obtain. The method given in the article can also be extended into wide ranges of high speed data acquisition system such as Time domain reflectometer, and jitter analyzer etc.

Adaptive frequency-related mismatch calibration algorithm for TIADC

The frequency response mismatch among time-interleaved analog-to-digital converters (TIADC) systems different channels will degrade sampling accuracy. We propose a frequency mismatch algorithm, where compensation filter is designed basing on adaptive strategy. Adopted with this digital post-processing technique, the filter calibrates frequency-related mismatches effectively. Experimental results verify its effectiveness.

Key technology design of 6 GSPS high-speed digital storage oscilloscope

With the growth of the ADC sampling bandwidth and the DSP theory and techniques becoming more sophisticated, the time-domain test based on real-time sampling, such as digital storage oscilloscope, is emerging to the mainstream of electronic test development, and also gestating the important transformation on electronic instrumentation systems. However, the extreme dependence on sampling rate and the rapidly inflated amount of information processing already become the time-domain tests bottleneck, and it greatly restricts the broadband time-domain test equipments development and application. This paper introduced design method of a broadband high speed digital storage oscilloscope, including design objectives, the overall scheme and work flow, and accessed the results of the experimental testing and analysis.