Network


Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot


Dive into the research topics where Huei Chaeng Chin is active.

Publication


Featured researches published by Huei Chaeng Chin.


Nanoscale Research Letters | 2014

Analytical modeling of glucose biosensors based on carbon nanotubes

Ali Hosseingholi Pourasl; Mohammad Taghi Ahmadi; Meisam Rahmani; Huei Chaeng Chin; Cheng Siong Lim; Razali Ismail; Michael Loong Peng Tan

In recent years, carbon nanotubes have received widespread attention as promising carbon-based nanoelectronic devices. Due to their exceptional physical, chemical, and electrical properties, namely a high surface-to-volume ratio, their enhanced electron transfer properties, and their high thermal conductivity, carbon nanotubes can be used effectively as electrochemical sensors. The integration of carbon nanotubes with a functional group provides a good and solid support for the immobilization of enzymes. The determination of glucose levels using biosensors, particularly in the medical diagnostics and food industries, is gaining mass appeal. Glucose biosensors detect the glucose molecule by catalyzing glucose to gluconic acid and hydrogen peroxide in the presence of oxygen. This action provides high accuracy and a quick detection rate. In this paper, a single-wall carbon nanotube field-effect transistor biosensor for glucose detection is analytically modeled. In the proposed model, the glucose concentration is presented as a function of gate voltage. Subsequently, the proposed model is compared with existing experimental data. A good consensus between the model and the experimental data is reported. The simulated data demonstrate that the analytical model can be employed with an electrochemical glucose sensor to predict the behavior of the sensing mechanism in biosensors.


Journal of Nanomaterials | 2014

Enhanced Device and Circuit-Level Performance Benchmarking of Graphene Nanoribbon Field-Effect Transistor against a Nano-MOSFET with Interconnects

Huei Chaeng Chin; Cheng Siong Lim; Weng Soon Wong; Kumeresan A. Danapalasingam; Vijay K. Arora; Michael Loong Peng Tan

Comparative benchmarking of a graphene nanoribbon field-effect transistor (GNRFET) and a nanoscale metal-oxide-semiconductor field-effect transistor (nano-MOSFET) for applications in ultralarge-scale integration (ULSI) is reported. GNRFET is found to be distinctly superior in the circuit-level architecture. The remarkable transport properties of GNR propel it into an alternative technology to circumvent the limitations imposed by the silicon-based electronics. Budding GNRFET, using the circuit-level modeling software SPICE, exhibits enriched performance for digital logic gates in 16 nm process technology. The assessment of these performance metrics includes energy-delay product (EDP) and power-delay product (PDP) of inverter and NOR and NAND gates, forming the building blocks for ULSI. The evaluation of EDP and PDP is carried out for an interconnect length that ranges up to 100 μm. An analysis, based on the drain and gate current-voltage (- and -), for subthreshold swing (SS), drain-induced barrier lowering (DIBL), and current on/off ratio for circuit implementation is given. GNRFET can overcome the short-channel effects that are prevalent in sub-100 nm Si MOSFET. GNRFET provides reduced EDP and PDP one order of magnitude that is lower than that of a MOSFET. Even though the GNRFET is energy efficient, the circuit performance of the device is limited by the interconnect capacitances.


Journal of Nanomaterials | 2014

Performance evaluation of 14 nm FinFET-based 6T SRAM cell functionality for DC and transient circuit analysis

Wei Lim; Huei Chaeng Chin; Cheng Siong Lim; Michael Loong Peng Tan

As the technology node size decreases, the number of static random-access memory (SRAM) cells on a single word line increases. The coupling capacitance will increase with the increase of the load of word line, which reduces the performance of SRAM, more obvious in the SRAM signal delay and the SRAM power usage. The main purpose of this study is to investigate the stability and evaluate the power consumption of a 14nm gate length FinFET-based 6T SRAM cell functionality for direct current (DC) and transient circuit analysis, namely, in resistor-capacitor (RC) delay. In particular, Berkeley Short-channel IGFET Model-Common Multigate (BSIM-CMG) model is utilized. The simulation of the SRAM model is carried out in HSPICE based on 14nm process technology. A shorted-gate (SG) mode FinFET is modeled on a silicon on insulator (SOI) substrate. It is tested in terms of functionality and stability. Then, a functional SRAM is simulated with 5GHz square wave at the input of word line (WL). Ideal square wave and square wave with 100 RC, 5 RC, 1 RC, and 0.5 RC are asserted to the WL and the bit lines (BL&BLB) of SRAM. Voltage at node q and q is observed. The simulation shows that 1 RC is the minimum square wave that will store correct value in node q and node q. Thus, this discovery from the research can be used as a modeling platform for circuit designers to explore and improve the SRAM tolerance against RC delay.


Journal of Nanomaterials | 2015

Design and performance analysis of 1-bit FinFET full adder cells for subthreshold region at 16 nm process technology

Aqilah binti Abdul Tahrim; Huei Chaeng Chin; Cheng Siong Lim; Michael Loong Peng Tan

The scaling process of the conventional 2D-planar metal-oxide semiconductor field-effect transistor (MOSFET) is now approaching its limit as technology has reached below 20 nm process technology. A new nonplanar device architecture called FinFET was invented to overcome the problem by allowing transistors to be scaled down into sub-20 nm region. In this work, the FinFET structure is implemented in 1-bit full adder transistors to investigate its performance and energy efficiency in the subthreshold region for cell designs of Complementary MOS (CMOS), Complementary Pass-Transistor Logic (CPL), Transmission Gate (TG), and Hybrid CMOS (HCMOS). The performance of 1-bit FinFET-based full adder in 16-nm technology is benchmarked against conventional MOSFET-based full adder. The Predictive Technology Model (PTM) and Berkeley Shortchannel IGFET Model-Common Multi-Gate (BSIM-CMG) 16 nm low power libraries are used. Propagation delay, average power dissipation, power-delayproduct (PDP), and energy-delay-product (EDP) are analysed based on all four types of full adder cell designs of both FETs. The 1-bit FinFET-based full adder shows a great reduction in all four metric performances. A reduction in propagation delay, PDP, and EDP is evident in the 1-bit FinFET-based full adder of CPL, giving the best overall performance due to its high-speed performance and good current driving capabilities.


Science of Advanced Materials | 2014

Nanoscale Device Modeling and Circuit-Level Performance Projection of Top-Gated Graphene Nanoribbon Field-Effect Transistor for Digital Logic Gates

Michael Loong Peng Tan; Huei Chaeng Chin; Li Len Lim; Weng Soon Wong; Eileen Lee Ming Su; Che Fai Yeong


Carbon | 2014

Extraction of nanoelectronic parameters from quantum conductance in a carbon nanotube

Huei Chaeng Chin; Arkaprava Bhattacharyya; Vijay K. Arora


Science of Advanced Materials | 2015

Top-of-the-barrier ballistic carbon nanotubes and graphene nanoribbon field-effect transistors quantum simulator

Huei Chaeng Chin; Chin Lin Ng; Cheng Siong Lim; Michael Loong Peng Tan


Science of Advanced Materials | 2014

Performance Benchmarking of 32 nm Predictive Technology Model CMOS with Silicon Nanowire Physic-Based Compact Model of Field-Effect Transistors for Digital Logic Applications

Huei Chaeng Chin; Nazril Hafiz Bin Mohamad; Michael Loong Peng Tan


Journal of Nanoelectronics and Optoelectronics | 2018

Performance Evaluation of 14 nm FinFET-Based 6T Static Random Access Memory Cell Functionality for DC and Transient Analysis

Kien Liong Wong; Huei Chaeng Chin; Chung Keong Chong; Cheng Siong Lim; Michael Loong Peng Tan


Journal of Nanoelectronics and Optoelectronics | 2018

Modeling and Simulation of the Electronic Properties in Graphene Nanoribbons of Varying Widths and Lengths Using Tight-Binding Hamiltonian

Edric Goh; Huei Chaeng Chin; Kien Liong Wong; Izzat Safwan Bin Indra; Michael Loong Peng Tan

Collaboration


Dive into the Huei Chaeng Chin's collaboration.

Top Co-Authors

Avatar
Top Co-Authors

Avatar

Cheng Siong Lim

Universiti Teknologi Malaysia

View shared research outputs
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar

Weng Soon Wong

Universiti Teknologi Malaysia

View shared research outputs
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar

Che Fai Yeong

Universiti Teknologi Malaysia

View shared research outputs
Top Co-Authors

Avatar

Chie Hou Leong

Universiti Teknologi Malaysia

View shared research outputs
Researchain Logo
Decentralizing Knowledge