Hui-I Wu

Complementary UWB LNA Design Using Asymmetrical Inductive Source Degeneration

This letter proposes a novel LNA design method where the complementary transistor topology is combined with asymmetrical inductive source degeneration to achieve matched input impedance over a wide bandwidth. A 2-10 GHz LNA is designed and fabricated using a commercial 0.18 RF-CMOS process to verify the feasibility of our proposed method. In the intended bandwidth, this LNA has matched input impedance, 20 dB power gain, and 2.4-3.4 dB noise figure, with 25.65 mW power consumption.

A 10~18GHz Wide-band Transformer feedback LNA

A wide-band (10~18 GHz) low noise ampIifier (LNA) is presented . With transformer feedback in the traditional cascode amplifier, good input matching is achieved from 10 GHz to 18 GHz. The noise figure is below 3.5 dB over 10-18 GHz. There is no input-matching elements in the input gate of the cascode amplifier, so that the LNA can achieve lower NF. The LNA is designed based on CMOS TSMC 0.18 mum mixed signal/RF process. With 1.8 V supply voltage and three stage amplifiers to achieve wider gain bandwidth, the LNA can achieve input-matching of -12 dB over the bandwidth; minimum NF 2.4 dB; gain (S21) of 17 dB and 1 dB gain compression (P1 dB) at -22.6 dB. The power consumption is 37.6 mW (exclude buffer).

A 1-V, Low-Power CMOS LNA for Ultra-wideband Receivers

A 1-V, low-power ultra-wideband (UWB) low-noise amplifier (LNA) for IEEE 802.15.3a is implemented in TSMC 0.18-mum mixed signal/RF CMOS process. With only IV bias voltage, the LNA can achieve a measured flat power gain (S21) of 10dB from 2.5 to 8.5 GHz while consuming only 7.25 mW. The minimum noise figure is 3.46dB. A simplified Chebyshev filter is used to achieve an input broadband matching of a measured Sll < -7.1dB from 3.1 to 10.6 GHz. An output-matching buffer is designed specially to match for high gain at upper frequency, the measured S22 is <-12.5dB from 3.1 GHz to 10.6 GHz. Furthermore, the high frequency electromagnetic effect of the transmission lines is considered in this circuit.

A Folded Current-Reused Down-Converter Mixer for Ultra Wide-Band Applications

This paper demonstrates an ultra-wideband mixer using TSMC 0.18 um mixed-signal/RF CMOS 1P6M technology. The main idea is to replace the traditional common source trans- conductance stage with a folded current-reused pair. It can enhance conversion power gain effectively without additional power consumption. And the folded approach is used to reduce supply voltage. To achieve wideband frequency response, second- order LC ladder wideband input matching network is utilized. This wide-band mixer achieves measured conversion power gain of 13.5-15.5 dB and a DSB noise figure of 11-14.5 dB from 3.1 GHz to 8 GHz. The dc power consumption is 11.25 mW under a supply voltage of 1.5 V, with a compact size of 0.83 mm2.

A 3-8 GHz RF Receiver Front-End for Multi-Band UWB Wireless System

This paper demonstrates a RF receiver front end circuit for multi-band orthogonal frequency division multiple access (MB-OFDM) using standard 0.18um complementery metal oxide semiconductor (CMOS) technology. The receiver front end includes a low-noise amplifier and a down conversion mixer. The proposed LNA uses transistors intrinsic capacitor Cgd and only one inductor as input matching network to achieve wideband impedance matching. And the proposed mixer uses folded current reused architecture to decrease supply voltage and enhance conversion power gain effectively. This wideband front end circuit achieves 19-21.5 dB of power gain and 4.3-6.2 dB of double-sideband (DSB) noise figure from 3.1GHz to 8 GHz with IF=100 MHz. The simulated core current consumption was 13.1 mA from a 1.5 V supply, with a compact size of 1.16 mm2.

Novel Wideband CMOS LNA with only an inductor as input matching network

A 3-8 GHz wide-band low noise amplifier with novel input matching mechanism is presented in this letter. The proposed circuit uses transistors intrinsic capacitor Cgd and only one inductor as input matching network to achieve a measured -10 dB input reflection coefficient from 2.75 GHz to 12 GHz. The fabricated wideband LNA achieves a measured average power gain (S21) of about 10 dB and noise figure of 3.64-5.5 dB from 2.75 to 7.5 GHz.

A New Sub-harmonic Mixer Using Switched Gm Technique For 802.11a/b/g Dual-Band Receivers

A new prototype of sub-harmonic mixer using switched Gm technique is designed and implemented in a standard 0.18 um CMOS technology. By using the PMOS active load and a switched Gm prototype at LO port, the new sub-harmonic mixer can achieve high conversion power gain and still maintain high linearity, and we can alleviate the shortage of the voltage headroom at IF output. In addition, it consumes no DC power while there is no LO input. At 5.2-GHz ISM band, this fully integrated sub-harmonic mixer achieves measured high conversion power gain of 12.8 dB, -1.8 dBm input third order intercept point (IIP3), and 14.0 dB noise figure at 10-MHz with 4 dBm LO power.

A Quadrature Voltage Controlled Oscillator with 9 Selective Bands for UWB Communication

A 9 bands quadrature voltage-controlled oscillator (QVCO) for UWB communciation operating from 2 to 10 GHz is presented. The architecture consists of a wideband quadrature voltage-controlled oscillator (QVCO), 2-stage dividers, switch buffer and only one quadrature single-sideband (SSB) mixer. Fabricated in 0.18-mum CMOS technology, this work achieves QVCOs measured phase noise less than -98 dBc/Hz at 1 MHz offset, and the simulated output powers of twelve bands have better than 35 dB sideband rejection while consuming 58.7 mW of the core circuit and 48.7 mW of the buffer from a 1.8-V supply. The simulated switching time for hopping frequency is about 1 ns.