Hui Yong Kim

Efficient In-Loop Filtering Across Tile Boundaries for Multi-Core HEVC Hardware Decoders With 4 K/8 K-UHD Video Applications

HEVC is a next generation video coding standard designed with modern coding techniques to be especially efficient for coding high-resolution video such as 4 K/8 K-ultra high- definition (UHD) video. Among the advanced coding tools of HEVC, tiles and wavefront parallel processing (WPP) have been newly adopted for parallel processing of such high-resolution (4 K/8 K-UHD) video. To realize UHD video services over portable devices with limited battery power, it is essential to implement multi-core-based and dedicated HEVC hardware decoders that support the tile- and wavefront-based parallel processing. By doing so, each frame is divided into a multiple number of picture partitions which can then be processed by multiple hardware decoder cores in parallel. However, in-loop filtering (ILF) at tile boundaries cannot be easily parallelized by a multi-core HEVC hardware decoder because of the data dependency between samples in different tiles. In this paper, an efficient control method for ILF across tile boundaries is proposed for multi-core HEVC hardware decoders. The proposed method does not require additional in-loop filters for ILF across the tile boundaries and it allows a decoder core to continue to process the next coding tree unit (CTU) without waiting for other decoders until they finish their ILF processing for the neighboring CTUs in other tiles. From experiments, we show the effectiveness of our ILF control method via a quad-core HEVC decoder for 4 K-UHD video implemented on a prototyping FPGA board.

A hierarchical variable-sized block transform coding scheme for coding efficiency improvement on H.264/AVC

In this paper, a rate-distortion optimized variable block transform coding scheme is proposed based on a hierarchical structured transform for macroblock (MB) coding with a set of the order-4 and −8 integer cosine transform (ICT) kernels of H.264/AVC as well as a new order-16 ICT kernel. The set of order-4, −8 and −16 ICT kernels are applied for inter-predictive coding in square (4×4, 8×8 or 16×16) or non-square (16×8 or 8×16) transform for each MB in a hierarchical structured manner. The proposed hierarchical variable-sized block transform scheme using the order-16 ICT kernel achieves significant bitrate reduction up to 15%, compared to the High profile of H.264/AVC. Even if the number of candidates for the transform types increases, the encoding time can be reduced to average 4–6% over the H.264/AVC

Variable Block Size Transforms with Higher Order Kernels for (Ultra) High Definition Video Coding

In this paper, 16-order and 32-order integer transform kernels are designed for the HD video coding in H.264|MPEG-4 AVC and the performance analyses for large transforms are presented. An adaptive block size transform coding scheme is also proposed based on the proposed transform kernels. Thus, additional 16-order (16 × 16, 16 × 8 and 8×16) and 32-order (32×32, 32×16 and 16×32) transforms are performed in addition to 8×8 and 4×4 transforms which are exploited in the Fidelity Range Extension of H.264|MPEG-4 AVC. The experimental results show that the variable block size transforms with the proposed higher order transform kernels yields 14.96% of bit saving in maximum for HD video sequences.

DMB Application Format for Mobile Multimedia Services

The Digital Multimedia Broadcasting Application Format-part 9 of the ISO/IEC 23000 MPEG-A Multimedia Application Formats standard-specifies a structured file format for securely packaging and interactively consuming DMB content.

Fast block mode decision scheme for B-picture coding in H.264/AVC

The recent H.264/AVC video coding standard provides a higher coding efficiency than previous standards. H.264/AVC achieves a bit rate saving of more than 50 % with many new technologies, but it is computationally complex. Most of fast mode decision algorithms have focused on Baseline profile of H.264/AVC which does not consider B-picture coding. In this paper, a fast block mode decision scheme for B-pictures in High profile and Main profile is proposed to reduce the computational complexity for H.264/AVC. To reduce the block mode decision complexity in B-pictures of High profile, we use the SAD value after 16×16 block motion estimation. This SAD value is used for the classification feature to divide all block modes into some proper candidate search block modes. A differential mode allocation method is also used for the list (list 0, list 1) of B-slices based on the SAD value of the 16 × 16 block mode. The proposed algorithm shows the average speed-up factors of 41.9 ∼ 58.57% for IBBPBB sequences with a negligible bit increment and a minimal loss of image quality.

Performance analysis of hierarchical transform coding with a large kernel for video codecs

In this study, the performance of hierarchical transform coding is analysed with design of an order-16 integer transform kernel. The proposed hierarchical transform-coding structure is constructed with a set of 4 × 4, 8 × 8 and 16 × 16 integer transforms of variable transform block sizes, which takes the advantages of both lower and higher transform kernels by flexibly adapting to varying image characteristics of video sequences with homogeneous and complex regions. The proposed hierarchical transform-coding structure is implemented as an extension to H.264/advanced video coding joint model. The authors show the effectiveness of the hierarchical variable-sized block transform scheme by analysing the quantisation effects and the correlation among neighbouring pixels in video sequences of different spatial resolutions. The experimental results show that: (i) the variable-sized block transform scheme with the hierarchical structure is advantageous to the texture regions with strong local edges and (ii) the higher-order-16 integer transform kernel itself is more effective for the homogeneous texture regions, which are often encountered in higher resolution sequences. Therefore these two features can complementarily work in an rate-distortion (RD) optimised manner for various characteristics of the input signals.

Understanding and Removal of False Contour in HEVC Compressed Images

A contour-like artifact called false contour is often observed in large smooth areas of decoded images and video. Without loss of generality, we focus on detection and removal of false contours resulting from the state-of-the-art High Efficiency Video Coding codec. First, we identify the cause of false contours by explaining the human perceptual experiences on them with specific experiments. Next, we propose a precise pixel-based false contour detection method based on the evolution of a false contour candidate (FCC) map. The number of points in the FCC map becomes fewer by imposing more constraints step by step. Special attention is paid to separating false contours from real contours such as edges and textures in the video source. Then, a decontour method is designed to remove false contours in the exact contour position while preserving edge/texture details. Extensive experimental results are provided to demonstrate the superior performance of the proposed false contour detection and removal method in both compressed images and videos.

Perceptual Quality Driven Frame-Rate Selection (PQD-FRS) for High-Frame-Rate Video

Video of higher frame rates (HFR) reduces the visual artifact in large screen display at the cost of a higher coding bit rate (or transmission bandwidth). In this work, we propose a perceptual quality driven frame rate selection (PQD-FRS) method that assigns a time-varying frame rate to a sequence so as to reduce its transmission cost. The objective of the PQD-FRS method is to offer perceptually indistinguishable experience for a certain percentage of viewers. We first conduct a subjective test to characterize the relationship between human perceived quality and video contents, and build a frame-rate-dependent video quality assessment dataset to serve as the ground truth. Then, we use a machine learning approach for the design of the key module of the PQD-FRS method, called the “satisfied user ratio (SUR) prediction.” The SUR prediction module predicts the percentage of satisfied viewers, who cannot differentiate video quality of a lower and HFR, using the support vector regression. It is confirmed by experimental results that the proposed SUR module can offer a so highly accurate prediction that the PQD-FRS system can dynamically assign a proper frame rate to video without any perceptual quality degradation for a majority of viewers.

CU-based Merge Candidate List Construction Method for HEVC

This paper proposes the CU-based approach for merge candidate list construction for providing reduced complexity and improved parallelism compared to the PU-based one. In the proposed method, a CU can have only one merge candidate list. So, Only one common merge candidate list is used for all PUs in a CU regardless of the PU partition type. The simulation results of proposed method showed that the encoder computational complexity was decreased by 3% to 6% and the decoder computational complexity was negligible change with the penalty of roughly 0.2% - 0.5% coding loss. The proposed method has several advantages: it provides simpler design, reduced complexity, and improved parallelism.

Coding Efficiency Improvement for Identical Motion Information of Bi-prediction Mode within the GPB Slcice of HEVC

This paper proposes the method which reduces complexity and improves coding efficiency by solving a problem of HEVC bi-prediction. In current HM 3.0, it is frequently occurred that L0 motion information and L1 motion information are identical in blocks which are bi-predicted. In this case, L1 motion vector is replaced by non-zero motion vector which belongs to first available neighbor block of current block. If they are still identical, prediction mode is replaced by uni-prediction. As an experimental result, in LD(Low-Delay) case, decoding time is reduced roughly 2%~5% and coding gain is roughly 0.3%~0.5% compared with the HM 3.0 anchor.