Huilong Zhu

Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs

Current drive enhancements were demonstrated in the strained-Si PMOSFETs with sub-100 nm physical gate lengths for the first time, as well as in the NMOSFETs with well-controlled threshold voltage V/sub T/ and overlap capacitance C/sub OV/ characteristics for L/sub poly/ and L/sub eff/ below 80 nm and 60 nm. A 110% enhancement in the electron mobility was observed in the strained Si devices with 1.2% tensile strain (28% Ge content in the relaxed SiGe buffer), along with a 45% increase in the peak hole mobility.

Sintering processes of two nanoparticles : a study by molecular-dynamics simulations

Molecular-dynamics computer simulations were employed to investigate the mechanisms of sintering of two single-crystal nanoparticles of Cu at a temperature of 700 K. Owing to their ultra-fine size ...

On the integration of CMOS with hybrid crystal orientations

Design and integration issues have been investigated for the hybrid orientation technology (HOT), i.e. device isolation, epitaxy and dopant implantation. Ring oscillators using HOT CMOS have been demonstrated for the first time, with L/sub poly/ about 85nm and t/sub ox/=2.2nm, resulting in 21% improvement compared with control CMOS on (100) orientations.

Strained Si CMOS (SS CMOS) technology: opportunities and challenges

Abstract Strain-induced enhancement of current drive is a promising way to extend the advancement of CMOS performance. Fabrication of strained Si MOSFET has been demonstrated with key elements of modern day’s CMOS technology. Significant mobility and current drive enhancements were observed. Recent advancements in the SS devices are summarized, and the challenges in device physics/design issues as well as in materials/process integration are highlighted.

A Simplified Hybrid Orientation Technology (SHOT) for high performance CMOS

A new concept in high performance VLSI called Simplified Hybrid Orientation Technology (SHOT) is introduced. This novel process flow creates circuits with independently oriented surface channels for pMOS and nMOS by integrating FinFETs with planar Ultra-Thin SOI (UTSOI) MOSFETs for the first time. The unique CMOS structure enables high mobility surface channel orientation for both devices. The SHOT scheme is also capable of producing PDSOI devices on the same chip. pFinFET drive current is among the best results reported (810 /spl mu/A//spl mu/m at V/sub dd/ = 1.2V).

Two-terminal vertical memory cell for cross-point static random access memory applications

In this work, the authors propose a 4F2 (F is the length of half pitch) memory cell with a vertical PNPN structure (silicon device with 4 layers doped with p-type, n-type, p-type and n-type dopants, respectively) to increase static random access memory (SRAM) integration density compared to the traditional 6T SRAM cell with an area of 90 ∼ 150F2. Thanks to the simple two-terminal configuration, the cross-point structure with proposed cell can be used in memory design, to achieve the highest density in planar complementary metal oxide semiconductor (CMOS) technology and to be implemented potentially in future three-dimensional integration. Experimental results demonstrate that the fabrication of proposed memory cell is compatible with CMOS process, little impact by process variation and reliability issues. Calibrated simulations display that the proposed cell can be programmed at nanosecond level speed with acceptable power consumption in most memory applications.

Enhanced End-Contacts by Helium Ion Bombardment to Improve Graphene-Metal Contacts

Low contact resistance between graphene and metals is of paramount importance to fabricate high performance graphene-based devices. In this paper, the impact of both defects induced by helium ion (He+) bombardment and annealing on the contact resistance between graphene and various metals (Ag, Pd, and Pt) were systematically explored. It is found that the contact resistances between all metals and graphene are remarkably reduced after annealing, indicating that not only chemically adsorbed metal (Pd) but also physically adsorbed metals (Ag and Pt) readily form end-contacts at intrinsic defect locations in graphene. In order to further improve the contact properties between Ag, Pd, and Pt metals and graphene, a novel method in which self-aligned He+ bombardment to induce exotic defects in graphene and subsequent thermal annealing to form end-contacts was proposed. By using this method, the contact resistance is reduced significantly by 15.1% and 40.1% for Ag/graphene and Pd/graphene contacts with He+ bombardment compared to their counterparts without He+ bombardment. For the Pt/graphene contact, the contact resistance is, however, not reduced as anticipated with He+ bombardment and this might be ascribed to either inappropriate He+ bombardment dose, or inapplicable method of He+ bombardment in reducing contact resistance for Pt/graphene contact. The joint efforts of as-formed end-contacts and excess created defects in graphene are discussed as the cause responsible for the reduction of contact resistance.

On the Control of Short-Channel Effect for MOSFETs With Reverse Halo Implantation

Reverse halo implantation (RHI), for the first time, is introduced and used to fabricate MOSFETs. It was demonstrated that RHI can dramatically improve short-channel effect, which can be used to enhance MOSFET performance, improve process control, or reduce stand-by power consumption. Implantation damage of RHI to gate oxide is negligible. The method of RHI is economic and suitable for massive manufacturing of very large scale integration

Device parameter optimization for sub-20 nm node HK/MG-last bulk FinFETs

Sub-20 nm node bulk FinFET PMOS devices with an all-last high-k/metal gate (HK/MG) process are fabricated and the influence of a series of device parameters on the device scaling is investigated. The high and thin Fin structure with a tapered sidewall shows better performance than the normal Fin structure. The punch through stop layer (PTSL) and source drain extension (SDE) doping profiles are carefully optimized. The device without SDE annealing shows a larger drive current than that with SDE annealing due to better Si crystal regrowth in the amorphous Fin structure after source/drain implantation. The band-edged MG has a better short channel effect immunity, but the lower effective work function (EWF) MG shows a larger driveability. A tradeoff choice for different EWF MGs should be carefully designed for the devices scaling.

Modeling of the diffusion of implanted boron in strained Si/Si/sub 1-x/Ge/sub x/

The diffusion of implanted boron in strained Si/Si/sub 1-x/Ge/sub x/ is investigated. A continuum segregation model (CSM) is presented to describe the phenomenon of B pile-up into the germanium profile. An analytic formula is obtained for Ge pre-amorphization and a modified pre-amorphization model is used in TSUPREM4 in order to accurately model our measurement data. Our simulations of boron diffusion are in reasonable agreement with our SIMS data. Comparison of the CSM with the model of immobile boron-germanium clusters is also discussed.