Huimei Yuan

Design and implementation of Costas loop based on FPGA

On the basis of analyzing the mathematical models of Costas loop, a method to model and simulate it by Simulink is put forward. In order to reduce the complexity of translating model to HDL (hardware description language), the model is realized by MATLAB code; the digital design of LPF (low-pass filter), LF (loop filter) and VCO (voltage-controlled oscillator) are mainly researched. At last, we accomplish the functional simulation by Verilog HDL code on Modlesim platform, finish the logic synthesis by synplify, and implement the hardware verification on the Cyclone series FPGA device EP1C6Q240C8 of Altera company. The final results are applied to the ASIC(application specific integrated circuit) design of BPSK (Binary Phase Shift Keying) signals demodulation. Results show that the Costas loop could correctly realize BPSK signals carrier recovery and data demodulation. Results of theoretical simulation and practical engineering experiments are the same. The method is proved simple, convenient and hardware resource saving.

Design and implementation of Digital Fuzzy-PID controller based on FPGA

In order to solve the problem of precise control of non-linearity system, a Digital Fuzzy-PID controller is designed by combining the advantages of fuzzy inference and PID controller based on FPGA. First, the model of the controller is established on the platform of Simulink. Simulation result shows that the controller exhibits a good transient response and a stable control action despite of the divergent controlled process. In the model, the control rules are established with the Fuzzy Logic Toolbox of MATLAB. Then the model is accomplished by VHDL using hierarchal and component design method. The controller is completed on Quartus II 8.0 by the technique of off-line calculation but online query processor. Finally, IP core of this controller is downloaded to the FPGA chip EP1C6Q240C8. Results of the experiment indicate that the operating speed of the controller is quick and the dynamic property of the control system has been improved evidently.

Optimized design of UART IP soft core based on DMA mode

This Traditional UART IP hard core is poor at flexibility and transportability while UART IP soft core is only based on poll and interrupt mode at present which consumes so much time of CPU that the performance of embedded system is reduced greatly. UART IP soft core based on DMA mode is proposed and well elaborated using the characteristic of DMA. The IP core is AVALON bus-compatible with the control and arithmetic logic of entire IP core completed by a single FPGA chip so that it is very suited to NIOSII embedded system. Five main sub modules are well designed and the whole IP core is tested and verified in a simple NIOSII embedded hardware system. It turns out that UART IP soft core based on DMA mode can reduce elapsed time of CPU greatly in data transmission process so that the performance of NIOSII system can be improved and design requirement can be better met with less resources occupied, high speed, high flexibility and high transportability.

Research on channel estimation for OFDM receiver based on IEEE 802.11a

Channel estimation is very important for suppressing interference and de-multiplexing signals. First, the structure of OFDM receiver system based on IEEE 802.11 a is established. Then, least square (LS) based channel estimation algorithm is mainly studied. Combing with the character of the preamble frame in IEEE 802.11a protocol, by using of the two long training symbol sequences in the frame preamble and de-noising technology with filters, a novel simple method to estimate channel is proposed. Simulations are done to the algorithm on some aspects such as the mean square error (MSE), constellation map of the demodulated data, bit error rate (BER) and the performance after de-noising with filters. Results show that this method could enhance the performance of the receiver in a certain level. At last, performances of the whole transceiver system based on IEEE 802.11a standard are simulated. It can be concluded that the performance of the OFDM receiver system is able to meet the requirement of IEEE 802.11a standard. Furthermore, the results prove the validity of our research on OFDM receiverpsilas channel estimation.

Design of CIC filter and DFC used in energy metering IC

Principles of CIC (cascade integrator comb) filter and DFC (digital-to-frequency converter) which is used in energy calculation are illustrated detailed in this paper. A new structure of 3-order CIC decimation filter is put forward in order meet the requirements of electric power metering chip, and a simple DFC method is presented in order to generate pulses proportional to the active power. VHDL is used to implement the two modules mentioned above and this design is verified on Alteras FPGA chip CycloneII EP2C35F484C8. At last, the design is applied in an electric power metering integrated chip. The calculation result shows that the design can improve precision of metering and stability of system. It is also improved that the design can save hardware resources and reduces costs.

FPGA realization of reactive power measurement system based on phase-shift

There are two ways to carry out phase-shift of reactive power measurement. One is based on the sampling points, the other is to use Hilbert filter. The two ways are designed and simulated with MATLAB in this paper. Hilbert filter is realized on EP2C50 series of EPGA, which has not been done by others so far. As statistics shows sampling points method has some limitations, while Hilbert Reactive Power Measurement is relatively more reliable and can ensure a more accurate result.

The research on phase-shift method of reactive power

Phase-shift method is one way of reactive power measurement, in the method, the input voltage or current is to phase-shift at first, then the multiplier which is used to calculate the active power will be used to calculate the reactive power. There are two ways to carry out phase-shift, the one is the way which is based on the sampling points, the other one is to use Hilbert filter. First of all, the principle of the two methods is expatiated in this paper, and then, they are designed and simulated on MATLAB, and the Hilbert filter method is verified on a FPGA chip of EP2C50 while there is no one else who has carried out the method on FPGA chip. The results show that the method based on sampling points is limited in practical application, but the Hilbert filter method has the advantages of Phase-shift accuracy and high precision measurement, it is used widely.

New symbol synchronization algorithms for OFDM systems based on IEEE 802.11a

Several new symbol timing synchronization algorithms for orthogonal frequency division multiplexing (OFDM) system based on IEEE802.11a are put forward. First, frame synchronization technology is studied in technology of symbol timing synchronization. According to the frame synchronization algorithm based on energy detection, an optimized algorithm named sliding window-counter algorithm based on two-sliding window algorithm is put forward, the optimized algorithm can provide more space between performance and resource consumption of ASIC realization; According to the frame synchronization algorithm based on cross correlation, a new algorithm of frame synchronization in multi-path fading channel, new solution is put forward by studying a period of long training symbol sequence in preamble. Simulation results show that these algorithms could finish accurate timing of symbol synchronization in worse channel.

Testing system design of individual Li-ion battery

At present, there are different kinds of individual battery test systems. In the area of traditional individual battery test systems, these systems are too big to carry and the price are too high. According to solving these problems, a new hardware design which is based on FPGA of Lithium Individual Cell Test System is creatively put forward in this paper. This kind of test system offers a way more powerful and flexibility and it is easier to operate. It has two modes which are automate enough that person can test battery by himself. It has been verified that the design could completely meet the requirement for high real-time performance and reliability and high accurate which will be with a bright prospect for the future.

FPGA realization of reactive power measurement system based on FFT

FFT is a kind of algorithms of reactive power measurement. It has high measurement precision and can be easily implemented on hardware. Now it is widely used in reactive power measurement. FPGA model of reactive power measurement based on FFT is put forward in this paper. Two ways to achieve FFT results are designed in this paper. One way is to use FFT IP core provided by Altera Company, and the other way is to design FFT by ourselves with programs. The system is implemented on EP2C50 series FPGA chips of Altera Company. Some characteristics of the system such as precision, speed and resource consumption are analyzed in details.