Husain Parvez

Exploration of heterogeneous FPGA architectures

Mesh-based heterogeneous FPGAs are commonly used in industry and academia due to their area, speed, and power benefits over their homogeneous counterparts. These FPGAs contain a mixture of logic blocks and hard blocks where hard blocks are arranged in fixed columns as they offer an easy and compact layout. However, the placement of hard-blocks in fixed columns can potentially lead to underutilization of logic and routing resources and this problem is further aggravated with increase in the types of hardblocks. This work explores and compares different floor-planning techniques of mesh-based FPGA to determine their effect on the area, performance, and power of the architecture. A tree-based architecture is also presented; unlike mesh-based architecture, the floor-planning of heterogeneous tree-based architecture does not affect its routing requirements due to its hierarchical structure. Both mesh and tree-based architectures are evaluated for three sets of benchmark circuits. Experimental results show that a more flexible floor-planning in mesh-based FPGA gives better results as compared to the column-based floor-planning. Also it is shown that compared to different floor-plannings of mesh-based FPGA, tree-based architecture gives better area, performance, and power results.

ASIF: Application Specific Inflexible FPGA

An Application Specific Inflexible FPGA (ASIF) is an FPGA with reduced flexibility that can implement a set of application circuits which will operate at mutually exclusive times. These circuits are efficiently placed and routed on an FPGA to minimize the total routing switches required by the architecture. Later all the unused routing switches are removed from the FPGA to generate an ASIF. An ASIF for a set of 17 MCNC benchmark circuits is found to be 5.43 times (81.5%) smaller than a mesh-based unidirectional FPGA required to map any of these circuits.

Application-Specific Mesh-based Heterogeneous FPGA Architectures

This book presents a new exploration environment for mesh-based, heterogeneous FPGA architectures. It describes state-of-the-art techniques for reducing area requirements in FPGA architectures, which also increase performance and enable reduction in power required. Coverage focuses on reduction of FPGA area by introducing heterogeneous hard-blocks (such as multipliers, adders etc) in FPGAs, and by designing application specific FPGAs. Automatic FPGA layout generation techniques are employed to decrease non-recurring engineering (NRE) costs and time-to-market of application-specific, heterogeneous FPGA architectures.

Application-Specific FPGA using heterogeneous logic blocks

This work presents a new automatic mechanism to explore the solution space between Field Programmable Gate Arrays (FPGAs) and Application-Specific Integrated Circuits (ASICs). This new solution is termed as an Application-Specific Inflexible FPGA (ASIF) [Parvez et al. 2009]. An ASIF can be considered as an FPGA with reduced flexibility, or as a reconfigurable ASIC that can implement a set of application circuits which will operate at mutually exclusive times. Execution of different application circuits can be switched by loading their respective bitstream on an ASIF. An ASIF that is reduced from a heterogeneous FPGA is termed as a heterogeneous ASIF. It is shown that a standard-cell-based heterogeneous ASIF for a set of 10 opencore application circuits is 9.6 times smaller than a single-driver mesh-based heterogeneous FPGA. The area gap between ASIC and ASIF is not too significant; however, it can be reduced by designing repeatedly used components of ASIF in full-custom. Unlike an ASIC, an ASIF is a reprogrammable device that can be used to reprogram new or modified circuits at a limited scale.

A new heterogeneous tree-based application specific FPGA and its comparison with mesh-based application specific FPGA

A heterogeneous Application Specific FPGA (ASIF) is a modified form of heterogeneous FPGA which is designed to explore the solution space between FPGAs and ASICs. Compared to an equivalent FPGA architecture, it has reduced flexibility but improved density. On the other hand, compared to an ASIC, it has reconfigurability but increased area. This work presents a new heterogeneous tree-based ASIF. Four ASIF generation techniques are explored for it using 17 benchmarks. Experimental results show that, on average, the best ASIF generation technique gives 70% area gain when compared to an equivalent FPGA architecture. Further experiments are performed to determine the effect of Lookup-Table (LUT) and arity size on heterogeneous tree-based ASIF. Later, area comparison between tree-based ASIF and equivalent mesh-based ASIF shows that the former gives either equal or better results than the latter. Finally quality comparison of two ASIFs shows that, on average, tree-based ASIF produces 18% better area results than mesh-based ASIF.

Comparison between heterogeneous mesh-based and tree-based application specific FPGA

An application specific FPGA (ASIF) is an FPGA with reduced flexibility and improved density. A heterogeneous ASIF is reduced from a heterogeneous FPGA for a predefined set of applications. This work presents a new tree-based heterogeneous ASIF and uses two sets of open core benchmarks to explore the effect of lookup table (LUT) and arity size on it. For tree-based ASIF, LUT size is varied from 3 to 7 while arity size is varied from 4 to 8 and 16. Experimental results show that smaller LUTs with higher arity sizes produce good area results. However, smaller LUTs produce worse results in terms of delay. Further experimental results show that for tree-based ASIF, the combination LUT 4 with arity 16 for SET I and LUT 3 with arity 16 for SET II gives best results in terms of area-delay product. Area comparison between mesh and tree-based ASIFs shows that tree-based ASIF gives 11.27% routing area gain for SET I and gives almost same area results for SET II while consuming 70.30% and 69.80% less wires for SET I and SET II benchmarks respectively. Finally the quality analysis shows that tree-based ASIF produces around 18% better results compared to mesh-based ASIF.

Application specific FPGA using heterogeneous logic blocks

An Application Specific Inflexible FPGA (ASIF) [12] is an FPGA with reduced flexibility that can implement a set of application circuits which will operate at different times. Application circuits are efficiently placed and routed on an FPGA in such a way that total routing switches used in the FPGA architecture are minimized. Later all unused routing resources are removed from the FPGA to generate an ASIF. An ASIF which is reduced from a heterogeneous FPGA (i.e. containing hard-blocks such as Multipliers, Adders and RAMS etc) is called as a Heterogeneous-ASIF. This work shows that a standard-cell based Heterogeneous-ASIF using Multipliers, Adders and Look-Up-Tables for a set of 10 opencores application circuits is 85% smaller in area than a single driver FPGA using the same blocks, and only 24% larger than the sum of areas of their standard-cell based ASIC version. If the Look-Up-Tables are replaced with a set of repeatedly used hard logic gates (such as AND gate, OR gate, flip-flops etc), the ASIF becomes 89% smaller than the Look-Up-Table based FPGA and 3% smaller than the sum of ASICs. The area gap between ASIF and sum of ASICs can be further reduced if repeatedly used groups of standard-cell logic gates in an ASIF are designed in full-custom. One of the major advantages of an ASIF is that just like an FPGA, an ASIF can also be reprogrammed to execute new or modified circuits, but at a very limited scale. A new CAD flow is presented to map application circuits on an ASIF.

A new coarse-grained FPGA architecture exploration environment

This paper presents an exploration environment for the design of 2D island-style coarse grained FPGA architectures. An architecture description file defines various architectural parameters including the definition of new coarse grained blocks, the positioning of blocks in the architecture and the selection of routing network. Once the initial architecture is defined, a software flow places and routes a target netlist on the generated architecture. The placement cost of a netlist is optimized either by changing the position of netlist instances on its respective blocks or by changing the position of blocks on the architecture. A single FPGA architecture can also be obtained for mapping a set of netlists at mutually exclusive times. It has been found that the sum of the placement costs of all the netlists is found to be minimum if all the netlists are used to get a single architecture. A set of DSP test-benches is used to show the effectiveness of the various techniques used in this work.

Generic techniques and CAD tools for automated generation of FPGA layout

This paper presents an automated method of generating an FPGA layout. The main purpose of developing a generator is to reduce the overall FPGA design time with limited area penalty. This generator works in two phases. In the first phase, it generates a partial layout using generic parameterized algorithms. The partial layout is generated to obtain a fast bitstream configuration mechanism, an efficient power routing and a balanced clock distribution network. In the second phase, the generator completes the remaining layout using automatic placer and router. This two-phase technique allows better maneuvering of the layout according to initial constraints. The proposed method is validated by generating the layout of an island-style FPGA which includes hardware support for the mitigation of Single Event Upsets (SEU). The FPGA layout is generated using a symbolic standard cell library which allows easy migration to any layout technology. This layout is successfully migrated to 130 nm technology.

Exploring the effect of LUT and arity size on a tree-based application specific inflexible FPGA

An application specific inflexible FPGA (ASIF) is an FPGA with reduced flexibility and improved density. An ASIF is reduced from an FPGA for a predefined set of applications that operate at mutually exclusive times. This work presents a new tree-based ASIF and uses a set of 16 MCNC benchmarks to explore the effect of lookup table (LUT) and arity size on it and results are then compared with those of mesh-based ASIF. For tree-based ASIF, LUT size is varied from 3 to 7 while arity size is varied from 4 to 8 and 16. Experimental results show that smaller LUTs with higher arity sizes produce good area results but poor performance results. Finally experimental results show that LUT 4 with arity 16 gives best area-delay product and compared to mesh-based ASIF, this combination gives 12% routing area gain.