Hüsnü Yenigün

Static Partial Order Reduction

A static partial order reduction generator and process result in a substantially reduced state space graph of a multi-process system, independently of the model checking process. The process of this invention creates a modified state graph generator with appended rules that allow any desired state searching tactic (breadth first, depth first, etc.) to be employed when states and transitions are considered in the course of verification. This permits use of existing model checking tools without needing to modify them. The static partial order reduction is made possible by realizing that a prior art condition that at least one state along each cycle of the reduced state graph must be fully expanded can be guaranteed by considering the individual processes that make up the system and identifying certain transitions in those processes.

Computer and information sciences-ISCIS 2006

This book constitutes the refereed proceedings of the 21st International Symposium on Computer and Information Sciences, ISCIS 2006, held in Istanbul, Turkey in October 2006. The 106 revised full papers presented together with 5 invited lectures were carefully reviewed and selected from 606 submissions. The papers are organized in topical sections on algorithms and theory, bioinformatics, computational intelligence, computer architecture, computer graphics, computer networks, computer vision, data mining, databases, embedded systems, information retrieval, mobile computing, parallel and distributed computing, performance evaluation, security and cryptography, as well as software engineering.

Testing Software and Systems

The talk will begin with a review of general testing concepts, such as white-box and black-box testing, different realizations of oracles (including a formal behavior specification), fault models and fault coverage issues, and testing architectures. This will set the framework for the following discussion which has two parts: (a) a discussion of the history of the ICTSS conference and the issues discussed during the early times since around 1985, and (b) an overview of two ongoing research projects: (1) on testing implementations against partial-order specifications, and (2) on reverse engineering of Rich Internet Applications for vulnerability testing. The first ICTSS conference was held in Vancouver (Canada) in 1988 and was called International Workshop on Protocol Test Systems. The main question discussed at that time was how to test a protocol implementation to ensure that it satisfies all requirements of a given protocol specification (a form of black-box testing). The main issues were the modeling language used for the specification, fault models, and algorithms for obtaining test suites with given fault coverage. At the same time, standardization committees of ISO and ITU developed guidelines for architectures for protocol testing and a language (TTCN) for specifying test cases. Later, the scope of ICTSS was broadened to cover the testing of many other kinds of software systems. In the second part of the talk, we will first discuss issues that arise in testing systems against a behavior specification that defines a partial order for the interactions of the implementation. Different partial-order specification languages will be considered. Then another ongoing research project on crawling Rich Internet Applications (RIAs) is discussed. Through the testing of a given implementation, a model of the RIA is developed (this is a kind of black-box testing, but without a reference specification). The purpose here is to obtain a “complete” model of the application such that each state (i.e. each page at the user interface) of the application can be subsequently checked for security vulnerabilities or accessibility requirements. Since the state space of these applications is usually huge, we propose (a) different algorithms for obtaining the most important information relatively fast, (b) concurrent exploration by multiple crawlers, and (c) some methods for avoiding the exploration of “equivalent” and “redundant” states. Formal Modeling and Testing for Designing Future IoT Based Systems

Theoretical aspects of computing - ICTAC 2008

This book constitutes the refereed proceedings of the 5th International Colloquium on Theoretical Aspects of Computing, ICTAC 2008 held in Istanbul, Turkey in September 2008. The 27 revised full papers were carefully reviewed and selected from over 70 submissions. The aim of the colloquium is to bring together practitioners and researchers from academia, industry and government to present research results, and exchange experience, ideas, and solutions for their problems in theoretical aspects of computing such as automata theory and formal languages, principles and semantics of programming languages, software architectures and their description languages, software specification, refinement, and verification, model checking and theorem proving, real-time, embedded and hybrid systems, theory of parallel, distributed, and internet-based (grid) computing, simulation and modeling, and service-oriented development.

2-D localization and identification based on SAW ID-tags at 2.5 GHz

An identification and localization system based on surface acoustic wave (SAW) radio sensors is presented in this paper. This system is able to identify and localize objects within a two-dimensional area. Identification is achieved with a fixed coded passive SAW identification-tag. Localization is carried out with three receiving antennas and with a following analysis of time delay between the sent interrogation signal and the received signals. For practical tests, a special interrogator has been established, as well as the receiving and demodulation unit. The whole system is controlled by a computer.

Eliminating redundant tests in a checking sequence

Under certain well–defined conditions, determining the correctness of a system under test (SUT) is based on a checking sequence generated from a finite state machine (FSM) specification of the SUT. When there is a distinguishing sequence for the FSM, an efficient checking sequence may be produced from the elements of a set Eα′ of α′-sequences that verify subsets of states and the elements of a set EC of subsequences that test the individual transitions. An optimization algorithm may be used in order to produce a shortest checking sequence by connecting the elements of Eα′ and EC using transitions drawn from an acyclic set. Previous work did not consider whether some transition tests may be omitted from EC. This paper investigates the problem of eliminating subsequences from EC for those transitions that correspond to the last transitions traversed when a distinguishing sequence is applied in an α′–sequence to obtain a further reduction in the length of a checking sequence.

Solving a robust airline crew pairing problem with column generation

In this study, we solve a robust version of the airline crew pairing problem. Our concept of robustness was partially shaped during our discussions with small local airlines in Turkey which may have to add a set of extra flights into their schedule at short notice during operation. Thus, robustness in this case is related to the ability of accommodating these extra flights at the time of operation by disrupting the original plans as minimally as possible. We focus on the crew pairing aspect of robustness and prescribe that the planned crew pairings incorporate a number of predefined recovery solutions for each potential extra flight. These solutions are implemented only if necessary for recovery purposes and involve either inserting an extra flight into an existing pairing or partially swapping the flights in two existing pairings in order to cover an extra flight. The resulting mathematical programming model follows the conventional set covering formulation of the airline crew pairing problem typically solved by column generation with an additional complication. The model includes constraints that depend on the columns due to the robustness consideration and grows not only column-wise but also row-wise as new columns are generated. To solve this difficult model, we propose a row and column generation approach. This approach requires a set of modifications to the multi-label shortest path problem for pricing out new columns (pairings) and various mechanisms to handle the simultaneous increase in the number of rows and columns in the restricted master problem during column generation. We conduct computational experiments on a set of real instances compiled from local airlines in Turkey.

Combining Software and Hardware Verification Techniques

Combining verification methods developed separately for software and hardware is motivated by the industrys need for a technology that would make formal verification of realistic software/hardware co-designs practical. We focus on techniques that have proved successful in each of the two domains: BDD-based symbolic model checking for hardware verification and partial order reduction for the verification of concurrent software programs. In this paper, we first suggest a modification of partial order reduction, allowing its combination with any BDD-based verification tool, and then describe a co-verification methodology developed using these techniques jointly. Our experimental results demonstrate the efficiency of this combined verification technique, and suggest that for moderate–size systems the method is ready for industrial application.

Verifying hardware in its software context

We describe a method for verifying hardware whose correct behaviour depends upon its software interface. It is presumed that the hardware is presented as a synchronous RTL model whereas the software is presented as an asynchronous abstraction. Our methodology incorporates partial order reduction on the software side, and localization reduction, to deal with the computational complexity of the verification. The partial order reduction is implemented as a constraint on the transition relation of a synchronous transformation of the software model. The reduced transformed model then may be verified using a verification algorithm whose scope is purely synchronous models, without modification. Thus, independent of the interface verification problem, this gives a general method for combining partial order reduction with symbolic model checking.

Design of an RFID-based Manufacturing Monitoring and Analysis System

Radio frequency identification (RFID) technology has become an important driver in the production and logistics activities of todays information-based industries and economies. With the innovative developments in information and communication technologies, companies focus more on how these changes can be implemented and promoted in order to improve their value-added processes. This paper presents one such implementation approach for the monitoring and analysis of a discrete manufacturing environment using the RFID technology. Our aim is to bridge the gap between the physical flow of materials on the shop floor and manufacturing information and execution systems by allowing a rapid development and deployment of an RFID-based manufacturing automation solution.