Huu Tuê Huynh

Performance analysis of a COFDM/FM in-band digital audio broadcasting system

In this paper, we present a performance analysis of a coded orthogonal frequency division multiplexing DAB system that is power multiplexed over a commercial FM station. We model the mobile channel with a time-frequency scattering function. Results show that the performance of the FM demodulator is crucial, since the level of the residual FM signal has a strong influence on the BER performance of the COFDM system. As with other mobile communication systems, the use of interleaving greatly enhances the performances.

Systematic design of pipelined recursive filters

Systematic design of pipelined recursive filters is presented. The procedure is based on a multiplication algorithm which generates the result with most significant digit first. Since the latency of such a multiplier is low, a reduced number of pipelining delays may be introduced in the reduction loop, resulting in a high sampling rate. The implementation obtained exhibits minimum hardware and ensures minimum latency. It is shown that its flexibility allows, on one hand, the ability to choose freely the number system radix and, on the other hand, the interleaving of two multiplier arrays into one. This is illustrated by the realization of a second-order all-pole filter, operating in a radix-4 representation and using only one array to perform two multiplications. In this way, long interconnections are avoided and denser and more regular layout is achieved. It turns out that the design procedure can also be applied successfully to various types of realization where multiplications are required. >

A new faster and simpler systolic structure for IIR filters

A bit-level systolic array architecture is presented for implementing infinite impulse response (IIR) filters. The topology is regular and modular, which makes the VLSI design easier. This realization has simpler hardware and a faster iteration period in comparison with a previous realization. In this case, the single coefficient of a one-pole filter covers the entire range of stability without increasing the array delay. Conventional full adders, multiplexers, and latches are the only type of base cell to be used in the array.<<ETX>>

A very fast digital realization of a time-domain block LMS filter

A novel digital implementation of time-domain block LMS (least mean square) filtering is presented. The primitive operators are serial-parallel multipliers which produce the results digit by digit, most significant first. The use of a redundant notation is essential here. These operators are placed in a parallel and pipeline structure, resulting in a fast realization with O(log(L*N) mod /sub L/) time, where N and L are filter length and block length, respectively. This new realization is particularly suitable for VLSI implementation because of this modularity and the high integration capacity of the serial-parallel multipliers.<<ETX>>

Fixed and multiple step power control for MC-DS-CDMA in indoor and outdoor environments

Power control is essential for code-division multiple-access CDMA cellular systems to overcome the near-far problem since all users share the same bandwidth. In this paper, we solve the power control problem for the multicarrier direct sequence CDMA (MC-DS-CDMA) system. We propose two algorithms based on the measure of the signal to interference ratio (SIR) allowing for the elimination of the effect of distance and slow shadowing in the case of indoor and outdoor environments.

Optimal detection of QAM in a man-made noise environment

It is known that in the personal communication systems environment, additive noise is not Gaussian. Experimental studies show that this type of noise obeys the class A Middleton man-made noise statistics. The influence of such noise is very severe on the probability error rate for a matched filter detector. To improve the detection performance, a non-linear detector should be used. This structure is based on the maximum likelihood approach which exploits multiple samples of the incoming signal. The improvement has been established by Spaulding and Middleton (1977) for the binary case. This paper generalizes this approach to M-ary signal detection, namely M-QAM, which is the most popular scheme in practice.

Turbo detection of turbo coded symbols over time varying frequency selective Rayleigh fading channel

This work deals with the transmission of turbo coded symbols in a frequency selective time varying channel. To reduce the channel effect, we use the turbo equalizer proposed in Laot et al. (2001). The equalizer consists of an intersymbol interference canceller and a MAP-BCJR decoder. Unlike Laot, where data information is convolutionally coded, in this paper, we use a turbo encoder. Thus, we have to redefine the channel reliability factor used by the MAP-BCJR decoding algorithm. We propose a new metric that takes into account the statistics of the signal at the equalizer output. Simulations show that the redefined channel reliability improves BER performance and the proposed equalizer is better than the classical DFE equalizer.

Influence of phase error on M-QAM demodulation in a non-Gaussian environment

This paper considers the influence of a deterministic phase error for coherent M-QAM demodulators in a non-Gaussian environment; the latter is modeled as a combination of a white Gaussian process and a filtered Poisson process whose enveloped amplitude obeys the Rayleigh distribution. General results show that when approaching the critical limit, the symbol error rate quickly reaches a plateau having a relatively large width.

Highly parallel architecture for the least mean squares (LMS) algorithm

A fast digital implementation for the least mean squares algorithm is proposed. The high concurrency of its structure allows for high processing speed with a sampling period of O(log N), where N is the number of filter taps. Chip area is minimized by the use of serial-parallel multipliers. In these multipliers, which use redundant arithmetic, the serial variables are transferred digit by digit, the most significant first.

Generalized DLMS algorithm

It is well known that a pipelined architecture helps the efficient implementation of the LMS algorithm. However, this type of architecture requires delays in the processing. In the open literature, the LMS algorithm with a single delay has been extensively studied. In this work, different types of delays are introduced into the architecture of the LMS algorithm. The influence of these delays on the algorithm behavior is analyzed theoretically and by simulations. Results lead to a number of constraints on the delays. The convergence conditions and the stationary residual error have also been obtained.