Huy-Hieu Nguyen

A Binary-Weighted Switching and Reconfiguration-Based Programmable Gain Amplifier

In previous works, the authors reported on binary-weighted switching and reconfiguration techniques to design programmable gain amplifiers (PGAs) with a wide decibel (dB)-linear range, a small gain error, a wide 3-dB bandwidth, and high linearity. In this brief, two techniques are analyzed in more detail. Adopting the two techniques, a new low-voltage PGA version is proposed that offers a precise and process/temperature-insensitive gain and achieves a double dB-linear range with a small gain error while maintaining the same chip size, as compared with those of previous designs. Implemented in 0.18-mum CMOS, from the measurements, the proposed PGA shows a dB-linear gain range of 42 dB (-21 to 21 dB) with a gain error of less than plusmn 0.54 dB, a maximum input-referred third-order intercept point (IIP3) of 14 dBm, and a 3-dB bandwidth of 60 MHz at the maximum gain while consuming only 2.1 mA from a 1.5-V supply.

A Self-Powered High-Efficiency Rectifier With Automatic Resetting of Transducer Capacitance in Piezoelectric Energy Harvesting Systems

This paper presents a self-powered rectifier for piezoelectric energy harvesting applications, and the key idea of the proposed system is to reset the transducer capacitor at optimal instants to maximize the extracted power. The proposed rectifier consists of two switches and two active diodes. The switches discharge the transducer capacitor at optimal instants two times for every cycle. The active diodes are based on op-amps with a preset dc offset, which reduces the voltage drop and the leakage current and avoids instability. In addition, the controller for the proposed rectifier is simple to reduce the circuit complexity and the power dissipation. The proposed rectifier was designed and fabricated in 0.18-μm CMOS technology. Measured results indicate that it achieves power efficiency of 91.2%, and the amount of power extracted by the proposed rectifier is 3.5 times larger when compared with the conventional rectifiers. The proposed rectifier does not require any off chip components to enable a full chip integration, and the die area of the proposed circuit is 0.08 × 0.20 mm2.

A high-linearity low-noise reconfiguration-based programmable gain amplifier

This paper presents a high-linearity low-noise small-size programmable gain amplifier (PGA) based on a new low-noise low-distortion transconductor and a proposed reconfiguration technique. The proposed transconductor combines an inverter-based differential pair with an adaptive biasing circuit to reduce noise and distortion. The reconfiguration technique saves the chip size by half and improves the bandwidth of the amplifier by utilizing the same differential pair for the input transconductance and load-stage, interchangeably. Fabricated in 0.18-μm CMOS, the proposed PGA shows a dB-linear control range of 21dB in 16 steps from −11dB to 10dB with a gain error of less than ±0.33dB, an IIP3 of 7.4÷14.5dBm, a P1dB of −7÷1.2dBm, a noise figure of 13dB, and a 3-dB bandwidth of 270MHz at the maximum gain, respectively. The PGA occupies a chip area of 0.04 mm2 and consumes only 1.3mA from the 1.8V supply.

A high efficiency piezoelectric energy harvesting system

Nowadays, harvested energy from surrounding environment plays an important role in the human life. This green energy gradually replaced for traditional energy such as fossil energy. Several methods have been used to capture green energy from environmental source. One of the most popular method is using piezoelectric material to harvest energy from vibration source. A piezoelectric energy harvesting system include two sections: a transducer to convert potential energy to the electrical energy and an electrical interface to manage this energy. Normally, a rectifier and voltage regulator are two main components in the electrical interface. In this paper, a new high efficiency piezoelectric energy harvesting system is proposed to increase extracted power from piezoelectric. By using two synchronized switches, the extracted efficiency of the rectifier is double. Furthermore, the passive diode of the conventional rectifier is replaced by active diode to increase the conversion efficiency of rectifier. The simulation result show that the power extraction efficiency of the rectifier is 3.5 times that of the conventional full bride rectifier, and more than 93% of power conversion efficiency can be achieved. To completely piezoelectric energy harvesting system a Low-drop regulator (LDO) is used to regulate voltage at the output of rectifier. The LDO gets maximum 90% efficiency with 3mV voltage ripple. The overall efficiency of proposed system gets 83.3%.

A rectifier for piezoelectric energy harvesting system with series Synchronized Switch Harvesting Inductor

In this paper, a rectifier with series Synchronized Switch Harvesting Inductor (Series SSHI) is proposed for piezoelectric (PE) energy harvesting system. The serial inductor helps to flip the voltage across the internal capacitor of the PE transducer instead of wasting the capacitor voltage by discharge. Active diodes are used for the switches to further improve the extraction efficiency. From measurements, the proposed rectifier shows a power extraction efficiency of 3.3 times that of the active full bridge (FB) rectifier, and more than 90% of the power conversion efficiency.

A High-Linearity Low-Noise Reconfiguration-Based Programmable Gain Amplifier

This paper presents a high-linearity low-noise small-size programmable gain amplifier (PGA) based on a new low-noise low-distortion transconductor and a proposed reconfiguration technique. The proposed transconductor combines an inverter-based differential pair with an adaptive biasing circuit to reduce noise and distortion. The reconfiguration technique saves the chip size by half and improves the bandwidth of the amplifier by utilizing the same differential pair for the input transconductance and load-stage, interchangeably. Fabricated in 0.18-μm CMOS, the proposed PGA shows a dB-linear control range of 21dB in 16 steps from −11dB to 10dB with a gain error of less than ±0.33dB, an IIP3 of 7.4÷14.5dBm, a P1dB of −7÷1.2dBm, a noise figure of 13dB, and a 3-dB bandwidth of 270MHz at the maximum gain, respectively. The PGA occupies a chip area of 0.04 mm2 and consumes only 1.3mA from the 1.8V supply.

A Piezoelectric Energy Harvester with High Efficiency and Low Circuit Complexity

This paper presents an efficient vibration energy harvester with a piezoelectric (PE) cantilever. The proposed PE energy harvester increases the efficiency through minimization of hardware complexity and hence reduction of power dissipation of the circuit. Two key features of the proposed energy harvester are (i) incorporation synchronized switches with a simple control circuit, and (ii) a feed-forward buck converter with a simple control circuit. The chip was fabricated in 0.18 μm CMOS processing technology, and the measured results indicate that the proposed rectifier achieves the efficiency of 77%. The core area of the chip is 0.2 mm2.

A new low-distortion transconductor applied in a flat band-pass filter

A new linearity improvement technique is proposed to implement a low-distortion Gm-C band-pass filter working in high IF ranges. The purpose of the linearization technique is to eliminate Gm″ value of the transconductor by employing a superposition method that combines two opposite non-linear behaviors of the two parallel wings designed inside the transconductor. Instead of conventional biquad structure, a resonant-coupling structure is adopted for the band-pass filter working at center frequency of 80MHz to make the frequency response flat and stable and to allow a stable frequency tuning as well as a flexible bandwidth tuning. Fabricated in 65nm CMOS process, the implemented IF band-pass filter provides a flat band-pass whose ripple is smaller than 0.1dB, a third-order rejection of 27dB, an IIP3 of −2dBm, and a NF of 21.5dB, while consuming 11mA from 1.2-V supply. The filter occupies a chip size of 0.5 mm × 0.5 mm.

Multiple-loop design technique for high-performance low dropout regulator

In portable mobile devices, the power management IC unit (PMIC) requires many low-dropout voltage regulators (LDO) with different output voltages and load current capacities to support many applications; such as Application Processor (AP), Camera, Memory, RFIC Transceivers, USB, etc. For example, the PMIC in mobile phone Galaxy S6/S7 needs more than 50 LDOs to support the above applications, which require an extremely big quiescent current that degrade battery life time. Reducing quiescent current of LDO while maintaining systems operation is critical; however, there is a big trade-off between quiescent current and other LDOs characteristics such as undershoot/overshoot, PSRR, noise, etc. This paper proposed a new multiple-loop design technique for LDO that offer very low quiescent current (more than 50% reduction); however, excellent performance improvement compared to prior reported works. The design has been successfully implemented in many products of Samsung for mobile phone, Table PCs, etc.

Correction to “An IF Bandpass Filter Based on a Low Distortion Transconductor” [Dec 10 2634-2646]

In the above titled paper (ibid., vol. 45, no. 12, pp. 2634-2646, Dec. 10), the authors made an error in Equation (10). The correct version of the equation is presented here.