Hyeon Jun Hwang

Fast transient charging at the graphene/SiO2 interface causing hysteretic device characteristics

Device instabilities of graphene metal-oxide-semiconductor field effect transistors such as hysteresis and Dirac point shifts have been attributed to charge trapping in the underlying substrate, especially in SiO2. In this letter, trapping time constants around 87 μs and 1.76 ms were identified using a short pulse current-voltage method. The values of two trapping time constants with reversible trapping behavior indicate that the hysteretic behaviors of graphene field effect transistors are due to neither charge trapping in the bulk SiO2 or tunneling into other interfacial materials. Also, it is concluded that the dc measurement method significantly underestimated the performance of graphene devices.

Effects of multi-layer graphene capping on Cu interconnects

The benefits of multi-layer graphene (MLG) capping on Cu interconnects have been experimentally demonstrated. The resistance of MLG capped Cu wires improved by 2-7% compared to Cu wires. The breakdown current density increased by 18%, suggesting that the MLG can act as an excellent capping material for Cu interconnects, improving the reliability characteristics. With a proper process optimization, MLG capped Cu interconnects could become a promising technology for high density back end-of-line interconnects.

Characteristics of CVD graphene nanoribbon formed by a ZnO nanowire hardmask

A graphene nanoribbon (GNR) is an important basic structure to open a bandgap in graphene. The GNR processes reported in the literature are complex, time-consuming, and expensive; moreover, the device yield is relatively low. In this paper, a simple new process to fabricate a long and straight graphene nanoribbon with a high yield has been proposed. This process utilizes CVD graphene substrate and a ZnO nanowire as the hardmask for patterning. 8 µm long and 50-100 nm wide GNRs were successfully demonstrated in high density without any trimming, and ∼ 10% device yield was realized with a top-down patterning process. After passivating the surfaces of the GNRs using a low temperature atomic layer deposition (ALD) of Al(2)O(3), high performance GNR MOSFETs with symmetric drain-current-gate-voltage (I(d)-V(g)) curves were demonstrated and a field effect mobility up to ∼ 1200 cm(2) V(-1) s(-1) was achieved at V(d) = 10 mV.

Enhanced Current Drivability of CVD Graphene Interconnect in Oxygen-Deficient Environment

Graphene has been considered as a candidate for interconnect metal due to its high carrier mobility and current drivability. In this letter, the breakdown mechanism of single-layer chemical-vapor-deposited (CVD) graphene and triple-layer CVD graphene has been investigated at three different conditions (air exposed, vacuum, and dielectric capped) to identify a failure mechanism. In vacuum, both single- and triple-layer graphenes demonstrated a breakdown current density as high as ~108 A/cm2, which is similar to that of exfoliated graphene. On the other hand, the breakdown current of graphene exposed to air was degraded by one order of magnitude from that of graphene tested in vacuum. Thus, oxidation initiated at the defect sites of CVD graphene was suggested as a major failure mechanism in air, while Joule heating was more dominant with dielectric capping and in vacuum.

Characteristics of a pressure sensitive touch sensor using a piezoelectric PVDF-TrFE/MoS2 stack

A new touch sensor device has been demonstrated with molybdenum disulfide (MoS2) field effect transistors stacked with a piezoelectric polymer, polyvinylidene fluoride-trifluoroethylene (PVDF-TrFE). The performance of two device stack structures, metal/PVDF-TrFE/MoS2 (MPM) and metal/PVDF-TrFE/Al2O3/MoS2 (MPAM), were compared as a function of the thickness of PVDF-TrFE and Al2O3. The sensitivity of the touch sensor has been improved by two orders of magnitude by reducing the charge scattering and enhancing the passivation effects using a thin Al2O3 interfacial layer. Reliable switching behavior has been demonstrated up to 120 touch press cycles.

Influence of extrinsic factors on accuracy of mobility extraction in graphene metal-oxide-semiconductor field effect transistors

Graphene has attracted attention because of its extraordinarily high mobility. However, procedures to extract mobility from graphene metal-oxide semiconductor transistors have not been systematically established because the accuracy of mobility value is affected by many extrinsic parameters. In this work, the influence of extrinsic parameters, such as contact resistance, transient charging effect, measurement temperature, and ambient on mobility are examined in order to provide a protocol capable of accurately assessing the mobility of graphene metal-oxide-semiconductor field effect transistors. Using a well controlled test protocol, the mobility of graphene is found to be temperature independent up to 450 K.

Electrical characteristics of wrinkle-free graphene formed by laser graphitization of 4H-SiC

Wrinkle free few layer graphene was demonstrated by a graphitization of 4H-SiC substrates using a high power pulsed KrF laser. Wrinkles often observed after thermal graphitization were eliminated with a short heat cycle using a pulse laser anneal. Few layer graphene formed by the laser graphitization appears to have a non-Bernal stack, which leads to on-off ratio of ∼2 even at a few layer graphene. Drive current of 143 μA/μm was obtained at Vd = 100 mV and field effect mobility was 374 cm2/Vs.

Correlation between the hysteresis and the initial defect density of graphene

The role of the initial defects of graphene characterized by Raman spectroscopy is correlated with the physical mechanisms causing the hysteretic device characteristics of graphene field effect transistors (FETs). Fast charging related to the tunneling-induced charge exchange is found to be closely correlated with the initial defect density, while slow charging related to environmental influences such as the water redox reaction showed a weak correlation. It can be concluded that the intrinsic quality of graphene should be improved to minimize the hysteresis of graphene FETs even in an air-tight environment.

Charge loss in TANOS devices caused by Vt sensing measurements during retention

In TANOS stuctures in retention, the major decrease in the programmed threshold voltage is found to be caused by the Vt sensing (IdVg measurements) rather than by intrinsic charge loss (when no bias is applied). This Vt decrease can be understood within the process of the temperature-activated charge transport through the Al2O3 blocking oxide. The charge loss can be minimized when Vt sensing time is decreased down to micro seconds. Blocking oxides engineered by adding a thin SiO2 layer at the SiN/AlO interface demonstrate significant suppression of the charge loss.

Contact resistance improvement by the modulation of peripheral length to area ratio of graphene contact pattern

High contact resistance between graphene and metal is a major huddle for high performance electronic device applications of graphene. In this work, a method to improve the contact resistance of graphene is investigated by varying the ratio of peripheral length and area of graphene pattern under a metal contact. The contact resistance decreased to 0.8 kΩ·μm from 2.1 kΩ·μm as the peripheral length increased from 312 to 792 μm. This improvement is attributed to the low resistivity of edge-contacted graphene, which is 8.1 × 105 times lower than that of top-contacted graphene.