Hyo-jung Song

Toward an Automatic Code Layout Methodology

This paper presents a study on an automatic code layout methodology for multi core architectures with explicit memory hierarchies. Code layout techniques are employed to run large programs on such systems. This study shows the effects of different buffer schemes and replacement policies on a set of benchmarks. These schemes are considered to be more flexible than current approaches. Moreover, these schemes can be used as a foundation to build frameworks for high level parallel programming models in such multi core architectures. The current work has been implemented in IBMs Cell Broadband Engine, but it can be extended to similar architectures.

A real-time media framework for asymmetric MPSoC

Multiprocessor-system-on-a-chips (MPSoCs) are being increasingly employed to solve a diverse spectrum of problems from both high-end and low-end computing. Multimedia streaming applications can get great performance from them, but developing MPSoC software that guarantees real-time requirements is very difficult. In this paper, we present an architecture of real-time media framework that can provide both easy of programming and real-time guarantee to multimedia applications. In addition, programming model and mechanism for real-time guarantee are briefly explained. Issues in developing media framework on asymmetric MPSoC hardware further presented, which we are going to apply in our media framework implementation

Parallelization and analysis of speech recognition on mobile multi-core processor

Speech recognition is an important application which requires large amount of computation and data. We parallelized speech recognition on ARM11-mpcore, one of the mobile multi-core processors. We achieved 1.92 times speed-up using four cores. We argue that this is sufficiently close to the theoretical best regarding Amdahls law. We also evaluated it on Intel Core2Quad to derive requirements for future mobile multi-core platforms.

Implementation of OpenMP Work-Sharing on the Cell Broadband Engine Architecture

The Cell Broadband Engine (CBE) is a single-chip multiprocessor composed of one Power Processor Element (PPE) core and multiple Synergistic Processor Element (SPE) cores. Due to the heterogeneous processor type of the CBE, multi-core programming for the CBE is very difficult which can be alleviated by OpenMP. In this paper, we introduce some issues in implementing OpenMP work-sharing constructs on the CBE. To address overheads in creating and managing work-sharing control blocks across different processor types, we have come up with a method for aggressively reusing the work-sharing control block by precisely checking the reusability of it. This scheme allows us better performance over naive implementation of work-sharing constructs, when evaluated with modified EPCC benchmark.