Hyoung-Joo Kim

Single-mode blue-violet laser diodes with low beam divergence and high COD level

We demonstrate GaN-based high-power single transverse-mode laser diodes (LDs) emitting at 405 nm. LD structures are designed to exhibit a high level of catastrophic optical damage and small beam divergence angle. By the control of refractive index profiles, we achieved a vertical beam divergence angle of as low as 17.5/spl deg/ and maximum output power of as high as 470 mW under continuous-wave operation condition. In addition, nearly fundamental transverse-mode operation is demonstrated up to 500-mW pulsed output power by far-field investigation.

25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation

The recent revolution in handheld computing with high-speed cellular network made mobile processors have multi-cores and powerful 3D graphic engines that support FHD (1920×1080) or even higher resolutions. Consequently, the memory bandwidth requirement has also been increasing, requiring a next-generation mobile DRAM standard. In this paper, we present a power-efficient LPDDR4 SDRAM operating at 3.2Gb/s/pin. Our LPDDR4 DRAM offers 2× bandwidth with improved power efficiency over LPDDR3 SDRAMs, due to the 2-channel architecture and low-voltage-swing terminated logic (LVSTL) [1]. Moreover, the supply voltage is further reduced to 1.0V in this work, 0.1V lower than the LPDDR4 standard, for extra power saving.

A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation

A 1.0 V 8 Gbit LPDDR4 SDRAM with 3.2 Gbps/pin speed and integrated ECC engine for sub-1 V DRAM core is presented. DRAM internal read-modify-write operation for data masked write makes the integrated ECC engine possible in a commodity DRAM. Time interleaved latency and IO control circuits enable 1.0 V operation at target speed. To reach 3.2 Gbps with improved power efficiency over conventional mobile DRAMs, the following IO features are introduced: Low voltage swing terminated logic drivers with VOH level calibration and periodic ZQ calibration, unmatched DQ/DQS scheme and DQS oscillator for DQS tree delay tracking. This chip is fabricated in 25 nm DRAM process on 88.1 mm 2 die area.

Fabrication of GaN Transistor on SiC for Power Amplifier

This letter presents the MISHFET with si-doped AlGaN/GaN heterostructure for power amplifier. The device grown on 6H-SiC(0001) substrate with a gate length of 180 nm has been fabricated. The fabricated device exhibited maximum drain current density of 837 mA/mm and peak transconductance of 177 mS/mm. A unity current gain cutoff frequency was 45.6 GHz and maximum frequency of oscillation was 46.5 GHz. The reported output power density was 1.54 W/mm and A PAE(Power Added Efficiency) was 40.24 % at 9.3 GHz.