Hyoungjun Cho

A FRAM technology using 1T1C and triple metal layers for high performance and high density FRAMs

Recently, ferroelectric random access memory has drawn a great deal of attention due to inherent properties such as nonvolatility, long retention time, high endurance, fast access time, small cell size compared to DRAM cell size in principle, and strong resistance to /spl alpha/-particle and cosmic ray irradiation. None of the available commercial memories meet all of the properties of the ferroelectric memory. Although ferroelectric memory has inherent good properties, full utilization of these properties has not yet been realized. Commercially available products are limited to low densities. The commercially available ferroelectric memory uses a 2T2C (two transistor-two capacitor) structure with single level metal instead of a 1T1C (one transistor-one capacitor) structure with multiple metal layers which is believed to be essential for mega-bit or giga-bit density memory. In this paper, an integration technology for high performance and high density FRAMs is developed using a 1T1C robust capacitor in a COB (capacitor over bit line) structure with triple metallization processes. The technology developed in this paper is evaluated with an experimental 4 Mb FRAM, which is the highest FRAM density developed to date.