Hyuk Kang

Enhancement of data retention and write current scaling for sub-20nm STT-MRAM by utilizing dual interfaces for perpendicular magnetic anisotropy

We investigate the sub-20nm level scalability of STT-MRAM cells possessing perpendicular magnetization induced from the interface of free layer (FL) and MgO tunnel barrier. We demonstrate that the MTJs utilizing dual interfaces of FL and MgO exhibit enhanced scalability with high thermal stability and low switching current, compared with the MTJs with a single interface. As thermal stability factor (Δ) varies as a function of MTJ dimension, MTJs with dual interfaces show Δ over 60 at 20nm node, while MTJs of single interface show Δ around 33. MTJs with dual interface also exhibit lower switching current per thermal stability (Ic/Δ), ~1/2 level of single interface MTJs.

Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications

10nm logic technology using Si FinFET is developed for low power and high performance applications. Power-speed gain of 27% compared to 14nm technology node was obtained using four key developments: 1) advanced gate stack engineering enabling 4 multi-Vt devices, 2) 3rd generation Fin technology, 3) highly doped source/drain (S/D), and 4) contact resistance optimization. CVD liner for BEOL process was also applied for better metal fill capability. Finally yield of the smallest ever SRAM with 0.04um2 SRAM bit-cell size was demonstrated.

MRAM with novel shaped cell using synthetic anti-ferromagnetic free layer

Magnetic random access memory (MRAM) with magnetic tunnel junction (MTJ) using synthetic anti-ferromagnetic (SAF) free layers of various shapes has been developed. SAF free layers show the predominance in the scalability compared with a conventional single free layer. It is also revealed that a novel shaped MTJ with a SAF free layer has a remarkably large writing margin.

Verification on the extreme scalability of STT-MRAM without loss of thermal stability below 15 nm MTJ cell

Scalability of interface driven perpendicular magnetic anisotropy (i-PMA) magnetic tunnel junctions (MTJs) has been improved down to 1X node which verifies STT-MRAM for future standalone memory. With developing a novel damage-less MTJ patterning process, robust magnetic and electrical performances of i-PMA MTJ cell down to 15 nm node could be achieved.

Thermally robust Ta-doped Ni SALICIDE process promising for sub-50 nm CMOSFETs

For sub-50 nm device application, Self-Aligned siLICIDE (SALICIDE) process by NiTa alloy has been developed for the first time. Use of NiTa-alloy makes nickel silicide on 50 nm gate thermally-robust up to 600/spl deg/C during device fabrication. NiTa SALICIDE process can also achieve excellent value and distribution of sheet resistance on 30 nm gate as well as low junction leakage current compared to Co SALICIDE. Furthermore, the drive current of PMOS is greatly increased. As a result, high-performance 90 nm MOSFETs is successfully integrated with NiTa SALICIDE process.

A novel simple shallow trench isolation (SSTI) technology using high selective CeO/sub 2/ slurry and liner SiN as a CMP stopper

A novel simple shallow trench isolation technology, SSTI, has been developed. SSTI consists of direct trench etching masked only with the photoresist, trench oxidation, liner SiN deposition, CVD oxide trench fill, densification, and high selectivity CMP. CMP stops at the liner SiN with a residual SiN thickness range of less than 2 nm and without micro-scratching. High selectivity CMP eliminates the field recess variation which is one of the drawbacks of conventional STI. SSTI is a promising candidate for future isolation technology.

Ge-redistributed poly-Si/SiGe stack gate (GRPSG) for high-performance CMOSFETs

A Ge-redistributed poly-Si/SiGe stack gate (GRPSG) has been proposed to improve the current performance of PMOS without the degradation of NMOS for sub-0.1 /spl mu/m CMOSFETs with ultrathin gate oxide. Ge diffusion into the poly-Si layer was promoted more by ion implantation of N-type dopants such as P and As rather than P-type dopants. NMOS and PMOS had different Ge concentrations at the interface between gate electrode and gate oxide by an additional anneal to redistribute the Ge profile. The current performance of NMOS with GRPSG with low Ge content (<5%) was not degraded, while that of PMOS with GRPSG with high Ge content (>20%) was improved due to suppression of the poly-depletion effect and boron penetration. In addition, the gate reoxidation was modified to reduce G/sub m/ degradation by reduced gate birds beak. High-performance 70 nm-CMOSFETs were successfully fabricated using the simple GRPSG process.

Channel engineering for 0.2 /spl mu/m surface channel pMOSFETs using electron beam irradiation

The electron beam (EB) irradiation process has been investigated to control the channel dopant profile of 0.2 /spl mu/m surface channel pMOSFETs for the first time. The results show that the channel dopants are redistributed along the EB-induced point defects by subsequent annealing when the EB is used to directly irradiate the pMOSFETs. As compared to the control process, EB treatment not only increases drive current by 14% but also reduces junction capacitance by 20% in pMOSFETs, despite the fact that EB treatment causes a reverse short channel effect. No degradation of the gate oxide reliability was identified for the EB treated sample.