Hyun-woo Park

Electromigration of NiSi poly gated electrical fuse and its resistance behaviors induced by high temperature

Insight is given on improved behaviors of the programmed NiSi polygated electrical fuse (eFuse) during the high temperature storage (HTS) test. By using a noble transmission electron microscopy (TEM) that includes scanning transmission electron microscopy (STEM), energy dispersive x-ray spectrometry (EDS), electron energy loss spectrometry (EELS) and nano-beam electron diffraction (NBED), microstructural behavior and phase transition of NiSi in the fuse link are painstakingly investigated before and after HTS test. It is found that improved post-resistance of eFuse is attributed to the low temperature growth of Ni3Si2 induced by HTS test at 250°C, which is microscopically proven by both ex-situ and in-situ TEM. In fact, Ni agglomeration, in which Ni resides around void formed in the fuse link, plays an important role of this cystallization. As results, the root causes of improved post-resistance of eFuse are qualitatively substantiated with respect to dynamic phase transformation and microstructural change in the fuse link.

Lower power Viterbi decoder architecture with a new clock-gating trace-back unit

This paper presents a new algorithm on lower-power survivor path memory implementation of the trace-back systolic array Viterbi algorithm. A novel idea is to reuse the already-generated trace-back routes to reduce the number of trace-back operations. It results in increasing the area of spurious switching activity region, and further reducing the switching activity with gated-clocks during trace-back operation. With the SYNOPSYS power estimation tool, DesignPower, our experimental result shows on the average 40% reduction in power with the same latency at a cost of 23% increase in area against the trace-back unit introduced by Truong et al. (1992). The proposed survivor memory scheme can be applied to the digital communication systems for targeting low power consumption.