Hyunbean Yi

Design of Test Access Mechanism for AMBA-Based System-on-a-Chip

A test interface controller (TIC) provided by ARM Ltd. is widely used for functional testing of system-on-a-chip (SoC) which adopts an advanced microcontroller bus architecture (AMBA) bus system. Unfortunately, this architecture has the deficiency of not being able to concurrently shift in and out the structural scan test patterns through the TIC and AMBA bus. This paper introduces a new AMBA based test access mechanism (ATAM) for speedy testing of SoCs embedding ARM cores. Since scan-in and out operations can be performed simultaneously, test application time on the expensive automatic test equipment (ATE) can be drastically reduced while preserving the compatibility with the ARM TIC.

Low-Cost Scan Test for IEEE-1500-Based SoC

In this paper, a reduced-pin-count-testing technique is presented to control the IEEE-1500 wrapper through the IEEE-1149.1 TAP for scan delay test. By using only the IEEE- 1149.1 TAP control pins as test-access pins and by embedding an on-chip test clock generator, low-cost automated test equipment (ATE) can be efficiently utilized to reduce testing costs. Experiments show the effectiveness of our technique in utilizing the ATE channels and scan delay testing.

Parallel CRC Logic Optimization Algorithm for High Speed Communication Systems

This paper presents a new optimization algorithm for designing parallel cyclic redundancy check (CRC) circuits widely adopted to detect burst errors in high-speed communications. Our heuristic algorithm is focused on minimizing the logic level and finding XOR terms shared as many as possible. An Ethernet 32-bit CRC generator, which was designed and mapped to FPGA and a standard cell library, shows the superiority of our approach in reducing the delay and area overhead

An efficient buffer allocation technique for virtual lanes in InfiniBand networks

InfiniBand Architecture(IBA) adopts a mechanism of Virtual Lanes(VL) to support various QoS, improve link utilization and avoid deadlock. IBA packets are placed in a buffer corresponding to each VL and are scheduled by a VL arbiter. Since the number of the packets through each VL may be different, the throughput can be improved by allocating buffers according to the packet characteristics. In this paper, a new buffer allocation scheme using VL arbitration table is proposed and the superiority of the network performance is shown through the simulation results.

Interconnect Delay Fault Test on Boards and SoCs with Multiple Clock Domains

This paper introduces an efficient interconnect delay fault test (IDFT) controller on boards and SoCs with IEEE 1149.1 and IEEE 1500 wrappers. By capturing the transition signals launched during one system clock, interconnect delay faults operated by different system clocks can be effectively tested with our technique. The IDFT controller proposed does not require any modification on boundary scan cells, instead very simple logic needs to be plugged around the TAP controller. Complete compatibility with the IEEE 1149.1 and IEEE 1500 standards is preserved and the superiority of this approach is verified through design experiments

Automated Cell Counting Method for HeLa Cells Image based on Cell Membrane Extraction and Back-tracking Algorithm

Cell counting is extensively used to analyze cell growth in biomedical research, and as a result automated cell counting methods have been developed to provide a more convenient and means to analyze cell growth. However, there are still many challenges to improving the accuracy of the cell counting for cells that proliferate abnormally, divide rapidly, and cluster easily, such as cancer cells. In this paper, we present an automated cell counting method for HeLa cells, which are used as reference for cancer research. We recognize and classify the morphological conditions of the cells by using a cell segmentation algorithm based on cell membrane extraction, and we then apply a cell back-tracking algorithm to improve the cell counting accuracy in cell clusters that have indistinct cell boundary lines. The experimental results indicate that our proposed segmentation method can identify each of the cells more accurately when compared to existing methods and, consequently, can improve the cell counting accuracy.

Design Reuse of on/off-Chip Bus Bridge for Efficient Test Access to AMBA-based SoC

This paper introduces an efficient test access mechanism for advanced microcontroller bus architecture (AMBA) based SoC to reduce the test application time while minimally adding a new test interface logic. Testable design technique is applied to an SoC with the advanced high-performance bus (AHB) and PCI bus bridge by maximally reusing the bridge functions. Testing time can be significantly reduced by increasing the test channels and by shortening the test control protocols. Experimental results show that area overhead and testing times in both functional and structural test modes are considerably reduced.