Hyunchol Shin

A 1.8-V 6/9-GHz reconfigurable dual-band quadrature LC VCO in SiGe BiCMOS technology

This paper presents a dual-band voltage-controlled oscillator (VCO) that can be reconfigured between 6- and 9-GHz frequency bands. It comprises a 6-GHz LC-tuned VCO, two 1/2 dividers, two mixers, and two 3-GHz notch filters. The 9-GHz output is generated based on the analog frequency multiplication method by mixing the 6-GHz VCO output with its divide-by-two signal. The VCO, implemented in a 0.18-/spl mu/m SiGe BiCMOS technology, achieves a fast reconfiguration time of 3.6 ns. The measured VCO phase noises are -106 and -104 dBc/Hz at 1-MHz offset for 6- and 9-GHz modes, respectively, while draining 10.8 mA from a 1.8-V supply.

A 1.8-V 6/9-GHz switchable dual-band quadrature LC VCO in SiGe BiCMOS technology

This paper presents a quadrature VCO that can be reconfigured between 6 and 9 GHz frequency bands. The dual-band VCO comprises a 6 GHz LC VCO, two 1/2-dividers, two mixers, and two 3 GHz notch filters. The 9 GHz output is generated based on a fractional frequency multiplication method by mixing the 6 GHz VCO output with its divide-by-two signal. The VCO, implemented in a 0.18 /spl mu/m SiGe BiCMOS technology, shows a fast switching time of 3.6 nsec. The measured VCO phase noises are -106 dBc/Hz and -104 dBc/Hz at 1 MHz offset for 6 and 9 GHz modes, respectively, while draining 10.8 mA from a 1.8 V supply.

A 2.7 Gb/s CDMA-interconnect transceiver chip set with multi-level signal data recovery for re-configurable VLSI systems

A 2.7 Gb/s interconnect transceiver chip-set based on Code Division Multiple Access (CDMA) is described and implemented in 0.18 /spl mu/m CMOS technology to achieve real-time system re-configurability and multiple I/O communication. The transceiver chip-set, with an Alexander-type multi-level data recovery circuit, can reconfigure multiple I/O signal routes within a symbol period of 0.8 ns. The chip-set dissipates 74 mW and occupies 0.3 mm/sup 2/ per I/O pair.

A 12-GHz GaInP/GaAs HBT VCO based on push-push output extraction from capacitive common-node

A new push-push VCO architecture takes the second harmonic output signal from a capacitive common-node in a negative-g/sub m/ oscillator topology. The generation of the 2nd harmonics is accounted for by the nonlinear current-voltage characteristic of the emitter-base junction diode causing; 1) significant voltage clipping and 2) different rising and falling time during the switching operation of core transistors. A prototype 12-GHz MMIC VCO realized in GaInP/GaAs HBT achieves an output power of -5 dBm, a phase noise of -108 dBc/Hz at 1 MHz offset while drawing 10.7 mA from a 2.4-V supply, which is equivalent to -175.8 dBc/Hz of VCO figure-of-merit.

A Delta-Sigma Fractional-N Frequency Synthesizer for Quad-Band Multi-Standard Mobile Broadcasting Tuners in 0.18-µm CMOS

A fractional-N frequency synthesizer supports quadruple bands and multiple standards for mobile broadcasting systems. A novel linearized coarse tuned VCO adopting a pseudo-exponential capacitor bank structure is proposed to cover the wide bandwidth of 65 %. The proposed technique successfully reduces the variations of KVCO and per-code frequency step by 3.2 and 2.7 times, respectively. For the divider and prescaler circuits, TSPC (true single-phase clock) logic is extensively utilized for high speed operation, low power consumption, and small silicon area. Implemented in 0.18-μm CMOS, the PLL covers 154 ~ 303 MHz (VHF-III), 462 ~ 911 MHz (UHF), and 1441 ~ 1887 MHz (L1, L2) with two VCO’s while dissipating 23 mA from 1.8 V supply. The integrated phase noise is 0.598 and 0.812 degree for the integer-N and fractional-N modes, respectively, at 750 MHz output frequency. The in-band noise at 10 kHz offset is -96 dBc/Hz for the integer-N mode and degraded only by 3 dB for the fractional-N mode.

RF-interconnect for multi-Gb/s digital interface based on 10 GHz RF-modulation in 0.18 /spl mu/m CMOS

Presents an RF-interconnect (RFI) for multi-Gb/s digital interface based on capacitive coupling and RF-modulation over an impedance-matched transmission line. The RFI can reduce the switching noise coupling greatly and eliminate the dc current dissipation completely over the channel. The improved signal-to-noise ratio enables data transmission with reduced signal swing (as low as 0.2 V) and potentially enhanced data speed. A prototype RFI implemented in 0.18 /spl mu/m CMOS demonstrates a maximum data rate of 2.2 Gb/s with 10.5 GHz RF-carrier.

A 9-GHz semi-dynamic frequency divide-by-2/3 in GaInP/GaAs HBT

A 9-GHz semi-dynamic frequency divide-by-2/3 circuit is presented. It comprises a Miller divider and a static divide-by-two in its feedback path. Unwanted harmonics are suppressed by adopting an image rejection Gilbert-cell mixer and an RC-CR phase shifter at the 9-GHz input port. Implemented in GaInP/GaAs HBT, the 2/3-divider operates over the input frequency range of 4.5-GHz to 9-GHz while it draws 61mA from a 4.2-V supply.

Design of a 2.4-GHz Fully Differential Zero-IF CMOS Receiver Employing a Novel Hybrid Balun for Wireless Sensor Network

A novel compact model for a five-port transformer balun is proposed for the efficient circuit design of hybrid balun. Compared to the conventional model, the proposed model provides much faster computation time and more reasonable values for the extracted parameters. The hybrid balun, realized in 0.18 ㎛ CMOS, achieves 2.8 ㏈ higher gain and 1.9 ㏈ lower noise figure than its passive counterpart only at a current consumption of 0.67 ㎃ from 1.2 V supply. By employing the hybrid balun, a differential zero-IF receiver is designed in 0.18 ㎛ CMOS for IEEE 802.15.4 ZigBee applications. It is composed of a differential cascode LNA, passive mixers, and active RC filters. Comparative investigations on the three receiver designs, each employing the hybrid balun, a simple transformer balun, and an ideal balun, clearly demonstrate the advantages of the hybrid balun in fully differential CMOS RF receivers. The simulated results of the receiver with the hybrid balun show 33 ㏈ of conversion gain, 4.2 ㏈ of noise figure with 20 ㎑ of 1/f noise corner frequency, and -17.5 ㏈m of IIP3 at a current consumption of 5 ㎃ from 1.8 V supply.

Enabling Technologies toward Fully LTE-Compatible Full-Duplex Radio

Full-duplex radio has potential to double spectral efficiency by simultaneously transmitting and receiving signals in the same frequency band, but at the expense of additional hardware and power consumption for self-interference cancellation. Hence, the deployment of a full-duplex cellular network can be realized by employing full-duplex functionality only at an eNodeB, which is supposed to have sufficient computation and power resources, and by scheduling pairs of half-duplex UEs that are in either downlink or uplink. By doing so, fast and smooth full-duplex deployment is possible while minimally affecting the legacy UEs and the rest of the network entities. In this article, we provide technical challenges and solutions for an LTE-compatible full-duplex cellular network, featuring wideband and wide dynamic range support for RF self-interference cancellation, and robust and efficient self-interference channel estimation for digital self-interference cancellation. Based on a realistic LTE-based cellular model, our full-duplex radio design is evaluated through system-level simulations and real-world testbed experiments. Simulation results show that a significant throughput gain can be achieved by the full-duplex technique despite the existence of physical limiting factors such as path loss, fading, and other-cell interference. Testbed measurements reveal that at a bandwidth of 20 MHz, self-interference cancellation up to 37 dB is achieved in the RF domain, and most of the residual self-interference is further cancelled down to the noise floor in the subsequent digital domain.

Design of a 40 GHz CMOS Phase-Locked Loop Frequency Synthesizer Using Wide-Band Injection-Locked Frequency Divider

This paper presents design of a 40 GHz CMOS PLL frequency synthesizer for a 60 GHz sliding-IF RF transceiver. For stable locking over a wide bandwith for a injection-locked frequency divider, an inductive-peaking technique is employed so that it ensures the PLL can safely lock across the very wide tuning range of the VCO. Also, Injection-locked type LC-buffer with low-phase noise and lowpower consumption is added in between the VCO and ILFD so that it can block any undesirable interaction and performance degradation between VCO and ILFD. The PLL is designed in 65 nm CMOS precess. It covers from 37.9 to 45.3 GHz of the output frequency. and its power consumption is 74 mA from 1.2 V power supply.