Hyungsoo Kim

Modeling and measurement of simultaneous switching noise coupling through signal via transition

The signal via is a heavily utilized interconnection structure in high-density System-on-Package (SoP) substrates and printed circuit boards (PCBs). Vias facilitate complicated routings in these multilayer structures. Significant simultaneous switching noise (SSN) coupling occurs through the signal via transition when the signal via suffers return current interruption caused by reference plane exchange. The coupled SSN decreases noise and timing margins of digital and analog circuits, resulting in reduction of achievable jitter performance, bit error ratio (BER), and system reliability. We introduce a modeling method to estimate SSN coupling based on a balanced transmission line matrix (TLM) method. The proposed modeling method is successfully verified by a series of time-domain and frequency-domain measurements of several via transition structures. First, it is clearly verified that SSN coupling causes considerable clock waveform distortion, increases jitter and noise, and reduces margins in pseudorandom bit sequence (PRBS) eye patterns. We also note that the major frequency spectrum component of the coupled noise is one of the plane pair resonance frequencies in the PCB power/ground pair. Furthermore, we demonstrate that the amount of SSN noise coupling is strongly dependent not only on the position of the signal via, but also on the layer configuration of the multilayer PCB. Finally, we have successfully proposed and confirmed a design methodology to minimize the SSN coupling based on an optimal via positioning approach

Suppression of GHz range power/ground inductive impedance and simultaneous switching noise using embedded film capacitors in multilayer packages and PCBs

We measured and demonstrated the great advantages of embedded film capacitors in reducing power/ground inductive impedance and the suppression of SSN at frequencies up to 3 GHz for high-performance multilayer packages and PCBs. Eight-layer test PCBs were fabricated, and their inductive power/ground network impedances were measured as a function of film thickness, via distribution, and combined use with discrete decoupling capacitors, using a two-port self-impedance measurement method. This successfully demonstrated that the power/ground inductive impedance was reduced from 270 pH to 106 pH simply by using an embedded film capacitor instead of 16 discrete decoupling capacitors.

High dielectric constant thin film EBG power/ground network for broad-band suppression of SSN and radiated emissions

We experimentally demonstrated the great advantages of a high dielectric constant thin film electromagnetic bandgap (EBG) power distribution network (PDN) for the suppression of power/ground noises and radiated emissions in high-performance multilayer digital printed circuit boards (PCBs). Five-layer test PCBs were fabricated and their scattering parameters measured. The power plane noise and radiated emissions were measured, investigated and related to the PDN impedance. This successfully demonstrated that the bandgap of the EBG was extended more than three times, covering a range of hundreds of MHz using a 1-cm /spl times/ 1-cm EBG cell, the SSN was reduced from 170 mV to 10 mV and the radiated emission was suppressed by 22 dB because of the high dielectric constant thin film EBG power/ground network.

Effects of on-chip and off-chip decoupling capacitors on electromagnetic radiated emission

Recently, electromagnetic interference (EMI) and radiated emission has become a major problem for high-speed circuit and package designers, and it is likely to become even severe in the future. However, until recently, designers of integrated circuit and package did not give much consideration to electromagnetic radiated emission and interference in their designs. Decoupling capacitors have been mostly used to reduce the power/ground bounce of high-speed digital system and boards. However, there has not been a systematic study to understand the effects of on-chip and off-chip decoupling capacitors on the electromagnetic radiated emission. In this paper, we report the simulation and the measurement results regarding the radiated emission due to the power/ground bounce. And we discuss the effects of the on-chip and off-chip decoupling capacitors to the power/ground bounce and the electromagnetic radiated emission. This circuit is simulated using HSPICE. Test ICs and printed circuit boards were designed and fabricated. Using a transverse electromagnetic (TEM) cell, the radiated electric field of the device under test (DUT) is measured. Combined placement of the on-chip and off-chip decoupling capacitor achieves more than 10 dB suppression of the radiated emission on the whole spectrum region. The design rule of the optimum placement of the decoupling capacitor was obtained.

Analysis and suppression of SSN noise coupling between power/ground plane cavities through cutouts in multilayer packages and PCBs

The authors introduced a model of simultaneous switching noise (SSN) coupling between the power/ground plane cavities through cutouts in high-speed and high-density multilayer pack-ages and printed circuit boards (PCBs). Usually, the cutouts are used in multilayer plane structures to isolate the SSN of noisy digital circuits from sensitive analog circuits or to provide multiple voltage levels. The noise-coupling model is expressed in terms of the transfer impedance. The proposed modeling and analysis results are compared with measured data up to 10 GHz to demonstrate the validity of the model. It is demonstrated that the cutout is the major gate for SSN coupling between the plane cavities, and that substantial SSN coupling occurs between the plane cavities through the cutout at the resonant frequencies of the plane cavities. The coupling mechanism and characteristics of the noise coupling, from which a method of suppression of the SSN coupling evaluated was also analyzed and discussed. Proper positioning of the cutout and the devices at each plane cavity achieves significant noise suppression at certain resonant frequencies. The suggested suppression method of the SSN coupling was successfully proved by frequency domain measurement and time domain analysis.

Embedded microstrip interconnection lines for gigahertz digital circuits

Transmission line structures are needed for the high-performance interconnection lines of GHz integrated circuits (ICs) and multichip modules (MCMs), to minimize undesired electromagnetic wave phenomena and, therefore, to maximize the transmission bandwidth of the interconnection lines. In addition, correct and simple models of the interconnection lines are required for the efficient design and analysis of the circuits containing the interconnection lines. In this paper, we present electrical comparisons of three transmission line structures: conventional metal-insulator-semiconductor (MIS) and the embedded microstrip structures-embedded microstrip (EM) and inverted embedded microstrip (IEM). In addition, we propose closed-form expressions for the embedded microstrip structures EM and IEM and validate the expressions by comparing with empirical results based on S-parameter measurements and subsequent microwave network analysis. Test devices were fabricated using a 1-poly and 3-metal 0.6 /spl mu/m Si process. The test devices contained the conventional MIS and the two embedded microstrip structures of different sizes. The embedded microstrip structures were shown to carry GHz digital signals with less loss and less dispersion than the conventional MIS line structures. S-parameter measurements of the test devices showed that the embedded microstrip structures could support the quasi-TEM mode propagation at frequencies above 2 GHz. On the other hand, the conventional MIS structure showed slow-wave mode propagation up to 20 GHz. More than 3-dB/mm difference of signal attenuation was observed between the embedded microstrip structures and the conventional MIS structure at 20 GHz. Finally, analytical RLCG transmission line models were developed and shown to agree well with the empirical models deduced from S-parameter measurements.

RF interconnect for multi-gbit/s board-level clock distribution

With clock distribution of over 1 GHz, problems associated with clock skew, power consumption, and timing jitter are becoming critical for determining the processing speed of high-performance digital systems, especially for multi-processor systems. Conventional digital clock distribution interconnection has a severe power consumption problem for GHz clock distribution because of the transmission line losses, as well as exhibiting difficult signal integrity problems due to clock skew, clerk jitter and signal reflection. To overcome conventional digital clock distribution limitations, optical clock distribution techniques, based on guided-wave optics and free-space optics, have been proposed. However, the optical clock distribution is found to be bulky, hard to fabricate, and expensive, even though it has lower power consumption and excellent signal integrity properties. In this paper, a multi-Gbit/s clock distribution scheme to minimize power consumption, skew, and jitter, based on RF interconnect technology, especially for the medium clock frequency region from 200 MHz to 10 GHz, and interconnection line lengths of from 10 cm to 3 m, is proposed. A quantitative comparison is made between the guided optical, the free-space optical, the conventional digital, and the proposed RF interconnections for board-level clock distribution relative to power consumption and speed. The proposed board-level clock distribution with 32-fan-outs has successfully demonstrated less than 22-ps skew and less than 3-ps jitter at 2 GHz. The estimated power consumption of the clock link for the proposed clock distribution has been shown to be about 320 mW. Furthermore, the proposed clock receiver using the RF clock distribution scheme has demonstrated less than 2-ps dead time and 3-ps skew time.

Significant reduction of power/ground inductive impedance and simultaneous switching noise by using embedded film capacitor

Significant reduction of power/ground inductive impedance and SSN suppression was successfully demonstrated by using embedded capacitor film in high performance package and PCB up to 3GHz frequency range. The reduction of the inductance impedance and SSN are acquired by the help of reduced via inductance in the embedded film capacitor.

Separated role of on-chip and on-PCB decoupling capacitors for reduction of radiated emission on printed circuit board

The power/ground fluctuation is known as a significant source of radiated emission. We discuss the separated functions of on-PCB and on-chip decoupling capacitors on the suppression of electromagnetic radiated emission. Due to the different ranges of parasitic inductance and the different locations of the on-chip current drivers, on-PCB and on-chip decoupling capacitors exhibit separated frequency characteristics in terms of suppression efficiency of radiation. The roles of on-PCB and on-chip decoupling capacitors are estimated by circuit simulation and a simple antenna model, and are confirmed by experiments. It is found that the on-chip decoupling capacitors are mainly effective for the suppression of radiated emission over 100 MHz frequency. Increase of the on-chip decoupling capacitance and decrease of the parasitic inductance of the package produce an improved suppression ratio at high frequency range. Combined placement and sizing of the decoupling capacitors have achieved more than 10 dB suppression of the electromagnetic radiated emission over a wide spectrum range.

3 GHz wide frequency model of ferrite bead for power/ground noise simulation of high-speed PCB

A reliable electrical model of a ferrite bead used in a real application field is crucially required by EMI field engineers for proper design of power supply and noise isolation. Especially, the model is needed for the power/ground noise simulation of multi-layer PCBs. In this paper a precise high-frequency model of a ferrite bead is reported up to 3 GHz. The proposed model was successfully verified with excellent agreement to experiment in terms of magnitude and phase of S-parameters, and Smith chart.