Hyunhee Kim

Lymphadenectomy increases the prognostic value of the revised 2009 FIGO staging system for endometrial cancer: a multi-center study.

BACKGROUND We investigated whether pelvic or para-aortic lymphadenectomy increases the prognostic value of the revised 2009 FIGO staging system in patients with endometrial cancer (EC). METHODS We reviewed 786 patients with EC from six tertiary medical centers between July 1996 and June 2008. All patients were classified according to the 1988 FIGO staging system: IA (n = 234); IB (n = 270); IC (n = 109); IIA (n = 35); IIB (n = 29); IIIA (n = 37); IIIB (n = 3); IIIC (n = 69), and the revised 2009 FIGO staging system was also applied to divide them: IA (=542); IB (=125); II (n = 29); IIIA (n = 18); IIIB (n = 3); IIIC1 (n = 43); IIIC2 (n = 26). Prognostic values between the 1988 and the revised 2009 FIGO staging systems were compared by multivariate Coxs proportional hazard analysis. RESULTS The 1988 FIGO stage IC, IIB, IIIA + IIIB and IIIC, and the revised 2009 FIGO stage IB, II, IIIA + IIIB and IIIC2 diseases were prognostic factors for poor PFS, whereas the 1988 FIGO stage IIB and IIIC, and the revised 2009 FIGO stage II, IIIA + IIIB and IIIC2 diseases were unfavorable prognostic factors for OS. Although these results were similar to those in 595 patients who underwent pelvic or para-aortic lymphadenectomy, the revised 2009 FIGO stage IIIC1 disease was an additional prognostic factor for poor PFS and OS (adjusted HRs, 4.19 and 11.25; 95% CIs, 1.39-12.60 and 2.23-36.74). CONCLUSIONS The revised 2009 FIGO staging system had a higher prognostic value than the 1988 FIGO staging system, and pelvic or para-aortic lymphadenectomy increased the prognostic value of the revised 2009 FIGO staging system for EC.

ePRO-MP: A tool for profiling and optimizing energy and performance of mobile multiprocessor applications

For mobile multiprocessor applications, achieving high performance with low energy consumption is a challenging task. In order to help programmers to meet these design requirements, system development tools play an important role. In this paper, we describe one such development tool, ePRO-MP, which profiles and optimizes both performance and energy consumption of multi-threaded applications running on top of Linux for ARM11 MPCore-based embedded systems. One of the key features of ePRO-MP is that it can accurately estimate the energy consumption of multi-threaded applications without requiring a power measurement equipment, using a regression-based energy model. We also describe another key benefit of ePRO-MP, an automatic optimization function, using two example problems. Using the automatic optimization function, ePRO-MP can achieve high performance and low power consumption without programmer intervention. Our experimental results show that ePRO-MP can improve the performance and energy consumption by 6.1% and 4.1%, respectively, over a baseline version for the co-running applications optimization example. For the producer-consumer application optimization example, ePRO-MP improves the performance and energy consumption by 60.5% and 43.3%, respectively over a baseline version.

A leakage-aware L2 cache management technique for producer-consumer sharing in low-power chip multiprocessors

This paper proposes a novel leakage management technique for applications with producer-consumer sharing patterns. Although previous research has proposed leakage management techniques by turning off inactive cache blocks, these techniques can be further improved by exploiting the various run-time characteristics of target applications in CMPs. By exploiting particular access sequences observed in producer-consumer sharing patterns and the spatial locality of shared buffers, our technique enables a more aggressive turn-off of L2 cache blocks of these buffers. Experimental results using a CMP simulator show that our proposed technique reduces the energy consumption of on-chip L2 caches, a shared bus, and off-chip memory by up to 31.3% over the existing cache leakage power management techniques with no significant performance loss.

Exploiting Replicated Cache Blocks to Reduce L2 Cache Leakage in CMPs

Modern chip multiprocessors (CMPs) employ large L2 caches to reduce the performance gap between processors and off-chip memory. However, as the size of an L2 cache increases, its leakage power consumption also becomes a major contributor to the total power dissipation. Managing the leakage power of L2 caches, therefore, is an important issue in realizing low-power CMPs. In CMPs with private L2 caches, each processor makes a copy of the data in its local cache in order to access the data faster, which is called replication. In this paper, we propose a novel leakage management technique that dynamically turns off replications in private L2 caches for leakage power reduction by exploiting two key observations: 1) the cost of an extra cache miss due to the turned-off replication is small because the same cache block exists in another on-chip cache and 2) turning off the replication incurs no extra cache miss if it is invalidated by other processors in order to maintain cache coherence. Since blindly turning off the frequently accessed replications can degrade performance, the proposed technique dynamically controls the number of turned-off replications. The proposed technique can be implemented by slightly modifying the MESI protocol with a new turned-off shared (TOS) coherence state. The TOS state indicates that the corresponding block is shared by other caches but turned off. Experiments on a four-processor CMP with private L2 caches show that the proposed technique reduces the energy consumption of the L2 caches and the main memory by 19.4% on average, with less than 1% performance loss over the existing cache leakage management technique.

Inhibition of platelet aggregation by 1-methyl-4-phenyl pyridinium ion (MPP+) through ATP depletion: Evidence for the reduced platelet activities in Parkinson's disease

Neuronal accumulation of 1-methyl-4-phenylpyridinium ion (MPP+), the metabolite of neural toxin, 1-methyl-4-phenyl-1,2,3,6-tetrahyropyridine (MPTP), induces a rapid depletion of cellular ATP level and loss of neuronal cell viability which simulates human Parkinsons disease (PD). Since ATP plays an important role in the physiology and function of platelets, which share many biochemical and physiological features with neuronal cells, we examined the effect of MPP+ on platelet aggregation and viability using freshly isolated rat platelets. While the treatment of MPP+ to platelets did not induce cytotoxicity, it significantly attenuated agonist-induced platelet aggregation in a concentration dependent manner. The inhibition of aggregation by MPP+ was mediated by the depletion of the cytoplasmic ATP pool and resultant decreased ATP secretion. Different from the previous reports in neuronal cells, MPP+ did not affect intracellular levels of glutathione and cytoplasmic Ca2+ in platelets. The combined treatment with MPP+ and 2-deoxyglucose, a glycolysis inhibitor, showed the additive effect in the decrease of ATP secretion and intracellular content. Consistent with these findings, inhibitory effects of MPP+ on platelet aggregation was significantly enhanced by the treatment with 2-deoxyglucose. In conclusion, these results suggested that MPP+ can induce ATP depletion in platelets and attenuate platelet aggregation providing a new theory on the reduced platelet activities in PD patients.

A reusability-aware cache memory sharing technique for high-performance low-power CMPs with private L2 caches

Chip multiprocessors (CMPs) emerge as a dominant architectural alternative in high-end embedded systems. Since off-chip accesses require a long latency and consume a large amount of power, CMPs are typically based on multiple levels of on-chip cache memories. To meet the performance demand and power budget, an efficient support for memory hierarchy is important. We propose an on-chip L2 cache organization which takes advantage of both a private L2 cache and a shared L2 cache to improve the performance and reduce energy consumption. Our L2 cache organization is based on a private L2 cache organization which has the short access latency. When a cache block in the private L2 cache is selected for an eviction, our proposed organization first evaluates the reusability of the cache block. If the cache block is likely to be reused, we save the evicted cache block in one of peer L2 caches which may have efficiently invalid blocks. By selectively writing evicted cache blocks to peer L2 caches, the proposed L2 cache organization can effectively simulate a shared L2 cache. Experimental results using a CMP simulator showed that the proposed L2 cache organization improved the average memory latency by up to 27% and reduced energy consumption by up to 16.6% over a 256KB private L2 cache organization for the SPLASH2 benchmark programs..

Replication-aware leakage management in chip multiprocessors with private L2 caches

Power dissipation has become a critical issue in modern chip multiprocessors (CMPs). Managing the leakage power of their L2 caches is particularly important in realizing low-power CMPs because most CMPs employ large L2 caches to hide the performance gap between processors and an off-chip memory while leakage power becomes a major portion in the total power dissipation of CMPs as process technology advances below 90 nm. We propose a replication-aware leakage management technique that selectively turns off a replicated block in a private L2 cache for leakage power reduction. Once a cache line is turned off, the data is lost, but its tag maintains the coherence state. The cost of an extra cache miss due to the turned-off replication is limited since the data of the cache line exists in another on-chip cache. Furthermore, the replicated block incurs no overhead if it is invalidated by other processors in order to maintain cache coherence. Our proposed technique can be implemented by slightly modifying the MESI protocol with a new turned-off shared coherence state. This state indicates that the corresponding block is shared by other caches but turned off. Experiments on a 4 processor CMP with private L2 caches show that the proposed technique reduces the energy consumption of the L2 caches and main memory by 20.0% on average without introducing significant performance loss over the existing cache leakage management technique.

A Low-Power Implementation of 3D Graphics System for Embedded Mobile Systems

For mobile 3D graphics systems, even though performance requirements are met, an efficient power management is even more important for battery-powered mobile devices since they require a large number of arithmetic operations as well as a high frequency of memory accesses. According to the analysis of the power consumption of mobile 3D graphics pipelines and the slacks across the pipeline stages, we describe intra-frame and inter-frame DVS low-power techniques reducing the power consumption of mobile devices based on a variable voltage processor. Our implementation on a PDA development board shows that the proposed DVS techniques achieve an energy saving of up to 46% over a non-DVS implementation

Reusability-aware cache memory sharing for chip multiprocessors with private L2 caches

In this paper, we propose a novel on-chip L2 cache organization for chip multiprocessors (CMPs) with private L2 caches. The proposed approach, called reusability-aware cache sharing (RACS), combines the advantages of both a private L2 cache and a shared L2 cache. Since a private L2 cache organization has a short access latency, the RACS scheme employs a private L2 cache organization. However, when a cache block in a private L2 cache is selected for eviction, RACS first evaluates its reusability. If the block is likely to be reused in the near future, it may be saved to a peer L2 cache which has space available. In this way, the RACS scheme effectively simulates the larger capacity of a shared L2 cache. Simulation results show that RACS reduced the number of off-chip memory accesses by 24% compared to a pure private L2 cache organization on average for the SPLASH 2 multi-threaded benchmarks, and by 16% for multi-programmed benchmarks.

A leakage-aware cache sharing technique for low-power chip multi-processors (CMPs) with private L2 caches

Power dissipation becomes an important issue in modern microprocessors such as chip multiprocessors (CMPs). Especially as the process technology advances below 90nm, the leakage power consumption becomes dominant in the total power dissipation, thus reducing the leakage power consumption is an important design goal for low-power CMPs. In particular, since most CMPs employ a large L2 cache, reducing the leakage power consumption of the L2 cache is critical in realizing low-power CMPs. In this paper, we propose a leakage-aware on-chip L2 cache organization called LACS. The proposed LACS, like the existing RACS organization, is based on a private L2 cache organization with an inter-L2 cache sharing support. However, unlike the RACS organization, which determines a peer L2 cache block for an inter-L2 cache sharing based on the reusability of the evicted L2 block and performance implications of peer L2 cache blocks, the LACS organization considers both the performance and leakage. The LACS organization reduces the leakage power consumption significantly over the leakage-oblivious RACS organization while achieving a similar performance gain over a private L2 cache organization. Experimental results show that the proposed LACS technique reduces the energy consumption by 23.6% and improves the energy delay product by 18.6% on average over the existing RACS scheme.