I. Hartimo

Heart sound segmentation algorithm based on heart sound envelogram

Desribes the development of a segmentation algorithm which separates the heart sound signal into four parts: the first heart sound, the systole, the second heart sound and the diastole. The segmentation of phonocardiogram (PCG) signals is the first step of analysis and the most important procedure in the automatic diagnosis of heart sounds. This algorithm is based on the normalized average Shannon energy of a PCG signal. The performance of the algorithm has been evaluated using 515 periods of PCG signals recording from 37 objects including normal and abnormal. The algorithm has achieved a 93 percent correct ratio.

Noise reduction in recursive digital filters using high-order error feedback

The problem of solving the optimal (minimum-noise) error feedback coefficients for recursive digital filters is addressed in the general high-order case. It is shown that when minimum noise variance at the filter output is required, the optimization problem leads to set of familiar Wiener-Hopf or Yule-Walker equations, demonstrating that the optimal error feedback can be interpreted as a special case of Wiener filtering. As an alternative to the optimal solution, the formulas for suboptimal error feedback with symmetric or antisymmetric coefficients are derived. In addition, the design of error feedback using power-of-two coefficients is discussed. The efficiency of high order error feedback is examined by test implementations of the set of standard filters. It is concluded that error feedback is a very powerful and versatile method for cutting down the quantization noise in any classical infinite impulse response (IIR) filter implemented as a cascade of second-order direct form sections. The high-order schemes are attractive for use with high-order direct form sections. >

Adaptive closed-loop power control algorithms for CDMA cellular communication systems

Power control has been widely studied and shown to be crucial for the capacity and performance of direct-sequence code-division multiple-access (DS-CDMA) systems. Practical implementations typically employ fast closed-loop power control, where transmitters adjust their transmit powers according to commands received in a feedback channel. The loop delay resulting from the measurements, processing, and transmission of the power control commands can result in oscillations of the transmission powers and lead to degradation in the system performance. In this paper we present new adaptive closed-loop power control algorithms that are able to alleviate the effect of the loop delay. The algorithms are based on self-tuning controllers designed for a log-linear model of the power control process. We carried out computational experiments on a DS-CDMA network using the distributed constrained power control (DCPC) as a reference algorithm. Practical versions of the algorithms are also provided and they were compared with the fixed-step power control (FSPC) algorithm employed in the IS-95 and WCDMA systems. The numerical results indicate that our algorithms can significantly improve the radio network capacity without any increase in power control signaling.

Delta operator realizations of direct-form IIR filters

The use of the delta operator in the realizations of digital filters has recently gained interest due to its good finite-word-length performance under fast sampling. We studied efficient direct form structures, and show that only some of them can be used in delta configurations, while others are evidently unstable. In this paper, we focus on the roundoff noise analysis. Of all the direct-form structures, the direct form II transposed (DFIIt) delta structure has the lowest quantization noise level at its output. This structure outperforms both the conventional direct-form (delay) structures, as well as the state-space structures for narrow-band low-pass filters with respect to output roundoff noise. Excellent roundoff noise performance is achieved at the cost of only a minor additional implementation complexity when compared with the corresponding delay realization. Complexity of a signal processor implementation of the DFIIt delta structure, which was found to be the most suitable delta structure for signal processors, is compared with those of the direct form and state-space delay structures. In addition, some hardware implementation aspects are discussed, including the minimization of the internal word length.

A heart sound feature extraction algorithm based on wavelet decomposition and reconstruction

An algorithm based on the wavelet decomposition and reconstruction method was developed to extract features from the heart sound recordings. An artificial neural networks classification method based on these features was used to classify the heart sound signals into physiological and pathological murmurs. The classification result indicated 74.4% accuracy.

A boundary modification method for heart sound segmentation algorithm

In this paper an improved algorithm for segmentation of phonocardiographic signal has been proposed. The algorithm is based on the use of spectrogram, which is calculated from the high-pass filtered phonocardiogram. The spectrogram is quantified to two values and projected to time axis to have the boundaries of heart events. In conclusion, more exact segmentation boundaries of the heart sound signal could be achieved and the performance of further analysis is improved.

Predictive power estimators in CDMA closed loop power control

The estimation of signal power is considered. Methods of designing optimized and partially-optimized power estimators, based on the Wiener model, for complex-valued signals are presented. Our application is a predictive received power level estimation in closed loop transmitter power control of mobile CDMA communications systems. The proposed estimators have the benefits of guaranteed positive output, high computational efficiency as compared to quadratic filters, and providing for a predescribed prediction step, all the aspects being of great interest when applying the estimators in delay sensitive closed control loops. The user capacity of a CDMA communications system is generally found to be greatly interference limited, and thus proper power control system functioning is of paramount interest. The partially-optimized power estimators are simulated along with Heinonen-Neuvo (1988) polynomial predictors in singleand multiuser CDMA uplink closed power control loop simulators.

Elimination of zero-input and constant-input limit cycles in single-quantizer recursive filter structures

A general criterion for the absence of zero-input limit cycles in digital filter structures that can be implemented with a single quantizer in the recursive loop is presented. The criterion can be applied to a rounding or magnitude truncation quantizer, and it allows the use of error feedback as well. Additionally, a method for the elimination of constant-input limit cycles is presented, provided that the implementation is already free from zero-input limit cycles. The criteria are applied to several well-known filter structures, and new results on their limit cycle properties in the single-quantizer configuration are obtained. It is shown that certain structures are always free from all zero-input and constant-input limit cycles when magnitude truncation is used for quantization. The single-quantizer structures can always be provided with appropriate error feedback, not only to achieve the elimination of limit cycles but also to reduce the roundoff noise, resulting in excellent overall performance. >

Design of optimum power estimator based on Wiener model applied to mobile transmitter power control

Estimation of signal power/instantaneous energy requires nonlinear systems. A power estimator based on the Wiener model is proposed in this paper. Its input signal can be complex-valued, e.g., a baseband signal in a communications system, and its output is guaranteed to be positive. It is computationally very efficient as compared to quadratic filters, and allows for a predescribed prediction step required, for example, for application in delay sensitive closed control loops. Two methods of optimum/partial-optimum design are presented. The partially-optimized power estimator is simulated in COSSAP environment as a part of the power control loop of a CDMA mobile radio communication system. The system performance improvements are observed from bit error rate reductions.

A novel double-decomposition method for systolic implementation of DFT

The authors discuss a novel systolic implementation of the discrete Fourier transform (DFT) algorithm by using a novel double-decomposition method to create two 4-point systolic preprocessors for a direct linear DFT implementation. The approach is well suited for large DFTs and reduces the number of required processors very effectively. The decomposition is carried out in two phases, first in the frequency and then in the time domain. With this double-decomposition, an N-point DFT can be implemented using sixteen N/16-point DFTs. A corresponding fully pipelined word-level systolic implementation is developed with time complexity O(N), in which only N/16+4 systolic processors are used in addition to 24 complex adders, three real adders, and five real multipliers. The elements of the systolic processors are of CORDIC (coordinate rotation digital computer)-type.<<ETX>>