I. Mamatha

Systolic architecture implementation of 1D DFT and 1D DCT

Discrete Fourier Transform is widely used in signal processing for spectral analysis, filtering, image enhancement, OFDM etc. Cyclic convolution based approach is one of the techniques used for computing DFT. Using this approach an N point DFT can be computed using four pairs of [(M-1)/2]-point cyclic convolution where M is an odd number and N=4M. This work proposes an architecture for convolution based DFT and its FPGA implementation. Proposed architecture comprises of a pre-processing element, systolic array and a post processing stage. Processing element of systolic array uses a tag bit to decide on the type of operation (addition/subtraction) on the input signals. Proposed architecture is simulated for 28 point DFT using ModelSim 6.5 and synthesized using Xilinx ISE10.1 using Vertex 5 xc5vfx100t-3ff1738 FPGA as the target device and can operate at a maximum frequency of 224.9MHz. The performance analysis is carried out in terms of hardware utilization and computation time and compared with existing similar architectures. Further, as the convolution based DCT has two systolic arrays similar to that of DFT, a unified architecture is proposed for 1D DFT/1D DCT.

Pipelined architecture for filter bank based 1-D DWT

A Convolution based parallel and pipelined architecture using MAC Loop Based Filter (MLBF) is proposed in this work. The proposed modification to the MLBF structure produces one output sample for every clock cycle as compared to the MLBF structure which produces two outputs for every four clock cycles. This results in a speed up of 2× which is significant for processing real time signals of long length. Compared to the existing MLBF based 1-D DWT architecture, proposed design uses additional 8 multipliers and 8 adders. The proposed structure is independent of the input size and filter length and performs better than other architectures with same or less area utilization. Generality, scalability, high efficiency of hardware utilization are the other merits of the proposed structure. The architecture is synthesized on Virtex 6 xc6vcx240t-2ff784 FPGA board and can operate at a maximum frequency of 633.43 MHz. The frequency of operation is twice as that of the existing approach.

Reduced Complexity Architecture for Convolution Based Discrete Cosine Transform

Discrete Cosine Transform is a popular transform used in signal/image processing applications. Reduction in complexity of hardware architecture for the computation of DCT using the convolution based algorithm is proposed. An N point DCT can be computed through 2 pair of [(M-1)/2] point cyclic convolutions where M is an odd number such that N=2M. The proposed architecture uses only a pair of systolic array where inputs are pipelined against the one in literature where 2 pairs of systolic arrays are used. One of the systolic arrays uses processing element with tag bit and the other one does not need a tag bit. The architecture uses 50% less number of processing elements with just an additional increase in computation time by one unit. The architecture is divided into three stages as preprocessor stage, compute stage where a systolic array computes the cyclic convolution and a post processing stage to process the output of the systolic array to get the actual DCT output. It is observed that the proposed architecture has a reduction of about 42%adders and 64% multipliers as compared to the one in literature. Further, the architecture is simulated in ModelSim 6.5 and synthesized using Xilinx ISE10.1using Vertex 5 FPGA as the target device. The simulation results are matched favourably with that of the output obtained by MATLAB R2010a with MSE of1.3861x10-4.

NEDA based hybrid architecture for DCT — HWT

Transforms are used in many signal processing applications. The VLSI implementation of a hybrid architecture to compute 8-point discrete cosine transform and Haar wavelet transform is proposed. The architecture is developed using NEw Distributed Arithmetic (NEDA) which is an efficient method for implementing inner products without using multipliers and ROM. The architecture developed is coded using Verilog HDL, simulated in ModelSim 6.4 and implemented using Xilinx ISE 14.7. Further, the hybrid architecture is implemented in 0.18μm CMOS technology using Cadence RTL compiler. Compared to standalone architectures, proposed architecture has 77.92% saving in register utilization, 41.80% savings in LUT utilization and 27.55% savings in number of adders used. The results show that the architecture is better in terms of power, hardware resources and complexity compared to earlier architectures.

Triple-Matrix Product-Based 2D Systolic Implementation of Discrete Fourier Transform

Realization of

Average current mode controlled DC - DC converter using digital controllers

N

Pre-regulated push pull converter for hybrid energy systems

N-point discrete Fourier transform (DFT) using one-dimensional or two-dimensional systolic array structures has been developed for power of two DFT sizes. DFT algorithm, which can be represented as a triple-matrix product, can be realized by decomposing