I. Ocaña

Adhesion Studies in Low‐k Interconnects Using Cross Sectional Nanoindentation

The thermo‐mechanical robustness of interconnect structures is a key reliability concern for integrated circuits. Cross‐sectional nanoindentation (CSN) was developed to characterize the interfacial adhesion in blanket films deposited on silicon substrates. Recently, this technique has been adapted to the study of adhesion failure in real interconnect structures. The method has been applied to test chips simulating a portion of the interconnect structure and it has proven useful to study local adhesion effects in patterned structures. The test has been modelled using an FE code and cohesive elements developed in house to improve the understanding of the crack path and its interaction with the different structures present in the interconnect stack.

Damage Induced in Interconnect Structures Mimicking Stresses During Flip Chip Packaging

Flip‐chip packages are produced by an interconnection technique in which the active area of a chip is mounted by various interconnecting materials on a multilayer substrate [1]. While flip‐chip technologies have progressed rapidly and are now widely used, they present special reliability concerns [2–4]. A large thermal expansion mismatch between the chip and the substrate increases the likelihood of fatigue failure in solder joints under cyclic thermal loading [2, 3]. In addition, the thermal mismatch often results in the delamination of interfaces between two materials, which eventually leads to mechanical and/or electrical failure [4]. In this paper piezo actuators are used to mimic stresses during packaging assembly and in operation. The test has been modeled using finite elements and the results show that the level of stresses reached during packaging can be attained. Electronic speckle‐pattern interferometry (ESPI) was applied for noncontact, real‐time evaluation of the deformation. Failure analysis ...