Ian D. Miller

Synthesizing hardware from dataflow programs: An MPEG-4 simple profile decoder case study

The MPEG Reconfigurable Video Coding working group is developing a new library-based process for building the reference codecs of future MPEG standards, which is based on dataflow and uses an actor language called CAL. The paper presents a code generator producing RTL targeting FPGAs for CAL, outlines its structure, and demonstrates its performance on an MPEG-4 Simple Profile decoder. The resulting implementation is smaller and faster than a comparable RTL reference design, and the second half of the paper discusses some of the reasons for this counter-intuitive result.

Synthesizing Hardware from Dataflow Programs

The MPEG Reconfigurable Video Coding working group is developing a new library-based process for building the reference codecs of future MPEG standards, which is based on dataflow and uses an actor language called Cal. The paper presents a code generator producing RTL targeting FPGAs for Cal, outlines its structure, and demonstrates its performance on an MPEG-4 Simple Profile decoder. The resulting implementation is smaller and faster than a comparable RTL reference design, and the second half of the paper discusses some of the reasons for this counter-intuitive result.

Automatic software synthesis of dataflow program: An MPEG-4 simple profile decoder case study

The MPEG reconfigurable video coding (RVC) framework is a new standard under development by MPEG that aims at providing a unified high-level specification of current MPEG video coding technologies. In this framework, a decoder is built as a configuration of video coding modules taken from the standard ldquoMPEG toolbox libraryrdquo. The elements of the library are specified by a textual description that expresses the I/O behavior of each module and by a reference software written using the CAL Actor Language. A decoder configuration is written in an XML dialect by connecting a set of CAL modules. Code generators are fundamental supports that enable the direct transformation of a high level specification to efficient hardware and software implementations. This paper presents a synthesis tool that from a CAL dataflow program generates C code and an associated SystemC model. Experimental results of the RVC Expertpsilas MPEG-4 simple profile decoder synthesis are reported. The generated code and the associated SystemC model are validated against the original CAL description which is simulated using the open dataflow environment.

Profiling dataflow programs

As dataflow descriptions of media processing become popular, the techniques for analyzing and profiling the performance of sequential algorithms are no longer applicable. This paper describes some of the basic concepts and techniques for analyzing the computations described by dataflow programs, and illustrates them on an MPEG-4 decoder.

An integrated environment for HW/SW co-design based on a CAL specification and HW/SW code generators

This demonstration presents an integrated environment that translates a CAL-based dataflow specification [1] into a heterogeneous implementation, composed by HDL and C codes. The demonstration focuses on the capability of the co-design environment to automatically build an executable heterogeneous system implementation running on a platform composed of a processor and a FPGA from the annotation of the CAL specification. The possibility of direct synthesis from a high level specification is a crucial issue for enabling efficient re-design cycles that include rapid prototyping and validation of performances of the final implementation. The design approach enabled by such integrated environment is particularly suited for development of complex processing systems such as video codecs. As a case study, the demonstration provides the analysis and validation of different software and hardware partitioning of a MPEG-4 Simple Profile decoder.

A Java development and runtime environment for reconfigurable computing

Fast runtime reconfigurable hardware enables system designers to swap hardware into and out of an FPGA much as-the pages of virtual memory are swapped into and out of virtual memory. Java provides a powerful object-oriented language with constructs to support multiple threads. In this paper, we discuss a method for developing reconfigurable hardware object class libraries, a runtime environment to manage these hardware objects and techniques for controlling such designs from the Java programming language.