Ian Grout

Simulation and construction of a speed control for a DC series motor

Abstract DC series motors are preferred for mechatronic applications requiring high torque/speed ratios. This paper describes the design and implementation of an open loop DC motor speed control that is based on a micro-controller and on IGBTs. Trial and error designs are expensive and time consuming. This problem is solved here by using simulation tools which can predict the dynamic behavior of systems consisting of mechanic and electronic modules. The simulations provided along the paper show a satisfactory agreement with laboratory measurements.

Defect-oriented vs schematic-level based fault simulation for mixed-signal ICs

Escalating demand for mixed-signal Integrated Circuits has been accompanied by the need to develop efficient strategies to guarantee higher quality at lower cost. One key to achieving this is efficient production test and the utilization of Design-for-Testability (DfT). Fault simulation based test evaluation would be a major contribution towards measuring and optimizing the effectiveness of a production test. Fault simulations, however, are only useful if the underlying fault list generation approaches accurately reflect manufacturing defects-both in their probability of occurrence and in their electrical behavior. This paper evaluates and compares two fault list generation approaches and the implications on test optimization. Fault lists derived from both Inductive Fault Analysis (IFA) and a transistor fault-model are compared for a testability analysis on a self-test function for a high-performance switched-current design.

Wide tuning-range CMOS VCO based on a tunable active inductor

In this paper, a wide tuning-range CMOS voltage-controlled oscillator (VCO) with high output power using an active inductor circuit is presented. In this VCO design, the coarse frequency is achieved by tuning the integrated active inductor. The circuit has been simulated using a 0.18-µm CMOS fabrication process and presents output frequency range from 100 MHz to 2.5 GHz, resulting in a tuning range of 96%. The phase noise is –85 dBc/Hz at a 1 MHz frequency offset. The output power is from –3 dBm at 2.55 GHz to +14 dBm at 167 MHz. The active inductor power dissipation is 6.5 mW and the total power consumption is 16.27 mW when operating on a 1.8 V supply voltage. By comparing this active inductor architecture VCO with general VCO topology, the result shows that this topology, which employs the proposed active inductor, produces a better performance.

Generating VHDL-AMS Models of Digital-to-Analogue Converters From MATLAB®/SIMULINK®

Today, the trend within the electronics industry is for the use of rapid and advanced simulation methodologies in association with synthesis toolsets. This paper presents an approach developed to support mixed-signal circuit design and analysis. The methodology proposed shows a novel approach to the problem of developing behavioral model descriptions of mixed-signal circuit topologies, by construction of a set of subsystems, that supports the automated mapping of MATLABreg/SIMULINKreg models to structural VHDL-AMS descriptions. The tool developed, named MS2SV, reads a SIMULINKreg model file and translates it to a structural VHDL-AMS code. It also creates the file structure required to simulate the translated model in the SystemVisiontrade. To validate the methodology and the developed program, the DAC08, AD7524 and AD5450 data converters were studied and initially modelled in MATLABreg/SIMULINKreg. The VHDL-AMS code generated automatically by MS2SV, (MATLABreg/SIMULINKreg to SystemVisiontrade), was then simulated in the SystemVisiontrade. The simulation results show that the proposed approach, which is based on VHDL-AMS descriptions of the original model library elements, allows for the behavioural level simulation of complex mixed-signal circuits.

An approach to realistic fault prediction and layout design for testability in analog circuits

This paper presents an approach towards realistic fault prediction in analog circuits. It exploits the Inductive Fault Analysis (IFA) methodology to generate explicit models able to give the probability of occurrence of faults associated with devices in an analog cell. This information intends to facilitate the integration of design and test phases in the development of an IC since it provides a realistic fault list for simulation before going to the final layout, and also makes possible layout optimization towards what we can call layout level design for testability.

A new quality estimation methodology for mixed-signal and analogue ICs

IC product quality is commonly described as the faulty device level at shipment and is becoming an increasingly important metric in the Microelectronics Industry. This paper presents and demonstrates a quality estimation approach based on Inductive Fault Analysis for mixed-signal and analogue ICs, that quantitatively models the quality related parameters prior to production. It is shown how the approach can be used to optimise the manufacturing test program.

Configuration and debug of field programmable gate arrays using MATLAB®/SIMULINK®

Increasingly, the need to seamlessly link high-level behavioural descriptions of electronic hardware for modelling and simulation purposes to the final application hardware highlights the gap between the high-level behavioural descriptions of the required circuit functionality (considering here digital logic) in commonly used mathematical modelling tools, and the hardware description languages such as VHDL and Verilog-HDL. In this paper, the linking of a MATLAB® model for digital algorithm for implementation on a programmable logic device for design synthesis from the MATLAB® model into VHDL is discussed. This VHDL model is itself synthesised and downloaded to the target Field Programmable Gate Array, for normal operation and also for design debug purposes. To demonstrate this, a circuit architecture mapped from a SIMULINK® model is presented. The rationale is for a seamless interface between the initial algorithm development and the target hardware, enabling the hardware to be debugged and compared to the simulated model from a single interface for use with by a non-expert in the programmable logic and hardware description language use.

Design and testing of a PI controller ASIC

This paper describes the design and testing of an application specific integrated circuit (ASIC) which provides the functionality of a digital proportional plus integral error actuated controller with auxillary feedback. The ASIC controller can provide discrete time control of a range of continuous time systems by receiving analogue inputs via a single multiplexed analogue to digital converter and providing an analogue output via a digital to analogue converter. The controller has a fixed sampling rate but allows both proportional and integral gains to be adjustable using a digital control word. The controller functions are performed in hardware on a single ASIC so providing for the same functionality as a software algorithm without the need for embedded software.

Remote laboratory experiment access via an RFID interface

In this paper, remote laboratory experiment access is considered through the use of radio frequency identification (RFID) technology. Contactless smart cards are used widely in many applications from travel cards through to building access control and inventory tracking. However, their use is considered here for access to electronic engineering experimentation in a remote laboratory setting by providing the ability to interface experiments through this contactless (wireless) connection means. A case study design is implemented to demonstrate such a means by incorporating experiment data onto a contactless smart card and accessing this via a card reader and web server arrangement.

Supporting access to STEM subjects in higher education for students with disabilities using remote laboratories

Remote laboratories have developed to an extent that they are now regularly used in the teaching and learning of the STEM (Science, Technology, Engineering and Mathematics) subjects within higher education institutions. The available resources of these remote laboratories and the user experience are usually designed with ease of access for students who do not have a disability - either a mental impairment or physical disability. However, the learning experience can be different between students who do not have a disability and students who have a disability. Therefore, the design of the learning experience should consider all potential users and be set-up so that a disability is not a barrier to full participation. This paper will consider the design and role of the remote laboratory in the student learning experience and will consider how the remote laboratory can be set-up to provide full access to all students.