Ian Page

Constructing hardware-software systems from a single description

The study of computing is split at an early stage between the separate branches that deal with hardware and software; there is also a corresponding split in later professional specialisation. This paper explores the essential unity of the two branches and attempts to point to a common framework within which hardware-software codesigns can be expressed as a single executable specification, reasoned about, and transformed into implementations. We also describe a hardware/software co-design environment which has been built, and we show how designs can be realised within this environment. A rapid development cycle is achieved by using FPGAs to host the hardware components of the system. The achitecture of a hardware platform for supporting experimental hardware/software co-designs is presented. A particular example of a real-time processing application built using this design environment is also described.

Reconfigurable processor architectures

Abstract No particular application is well-supported by a conventional microprocessor which has a pre-determined set of functional units. This is particularly true in highly dynamic areas, such as multimedia, communications and other embedded systems. We suggest that additional silicon is used to provide hardware which can be dynamically configured to support any application. By combining a conventional microprocessor and FPGA reconfigurable logic on one chip, commodity pricing is maintained and yet the same part can effectively support a wide range of applications. A novel FPGA architecture is outlined which is particularly suitable for this style of implementation.

Towards a Provably Correct Hardware Implementation of Occam

This paper shows how to compile a program written in a subset of occam into a normal form suitable for further processing into a netlist of components which may be loaded into a Field-Programmable Gate Array (FPGA). A simple state-machine model is adopted for specifying the behaviour of a synchronous circuit where the observable includes the state of the control path and the data path of the circuit. We identify the behaviour of a circuit with a program consisting of a very restricted subset of occam. Algebraic laws are used to facilitate the transformation from a program into a normal form. The compiling specification is presented as a set of theorems that must be proved correct with respect to these laws. A rapid prototype compiler in the form of a logic program may be implemented from these theorems.

The Design of a New FPGA Architecture

A new Field Programmable Gate Array (FPGA) architecture is described. This architecture includes a number of novel features not found in currently available FPGAs. It is believed to offer a significantly improved logic density in some common applications.

Using Reconfigurable Hardware to Speed up Product Development and Performance

Harp1 is a circuit board designed to exploit the rigorous compilation of parallel algorithms directly into hardware. It includes a transputer closely-coupled to a Field-Programmable Gate Array (FPGA). The whole system can be regarded as an instance of a process in the theory of Communicating Sequential Processes (CSP). The major elements themselves can also be viewed in the same way: both the transputer and the FPGA can implement many parallel communicating sub-processes. The Harp1 design includes memory banks, a programmable frequency synthesizer and several communication ports. The latter supports the use of parallel arrays of Harp1 boards, as well as interfacing to external hardware. Harp1 is the target of mathematical tools based upon the Ruby and occam languages, which enable unusual and novel applications to be produced and demonstrated correctly and rapidly; the aim is to produce high quality designs at low costs and with reduced development time.

Two parallel methods for polygon clipping

A control parallel and a novel data parallel implementation of the Sutherland‐Hodgman polygon clipping algorithm are presented. The two implementations are based on the INMOS transputer and the AMT Distributed Array Processor respectively; both of these machines are general purpose parallel processors. Performance Figures are reported and implications for further work are discussed.

A Self-Validating Temperature Sensor Implemented in FPGAs

A SEVA sensor is an intelligent device which monitors its own performance and generates quality indices for each measurement value, including its level of uncertainty. This paper describes a SEVA temperature sensor in which all the measurement uncertainty and validation calculations are carried out in FPGAs. Hardware compilation is used to configure the FPGAs to provide the required functionality.

Design of future systems

This paper describes a vision in which future systems consisting of novel hardware and software components are designed and implemented by a single type of professional engineer. That professional has more in common with todays programmer than a hardware designer, although both of these existing bodies of professionals have a strong contribution to make to understanding, defining and bringing about this transformation in product creation.

Constraint-based Hierarchical Placement of Parallel Programs

This paper continues our investigation into the feasibility of exploiting the structure of a parallel program to guide its hardware implementation. We review previous work, and present our new approach to the problem based upon placing netlists hierarchically. It is found that appropriate constraints can be derived from the source code in a straight-forward way, and this information can be used to guide the subsequent placement routines. Comparisons with traditional placement procedures based on simulated annealing are given.

Polygon rendering on a dual-paradigm parallel processor

Abstract The Disputer is a general purpose parallel processor which incorporates both Single Instruction Multiple Data stream (SIMD) and Multiple Instruction Multiple Data stream (MIMD) parallelism. It is shown how the polygon rendering operations of filling and hidden surface elimination can be efficiently distributed among the SIMD and the MIMD parts of the Disputer. Apart from being a useful graphics application, this work illustrates some of the issues involved in programming the Disputer efficiently and, in particular, the need to keep communication between the SIMD and the MIMD parts low.