Iason Vassiliou

A single-chip digitally calibrated 5.15-5.825-GHz 0.18-/spl mu/m CMOS transceiver for 802.11a wireless LAN

The drive for cost reduction has led to the use of CMOS technology in the implementation of highly integrated radios. This paper presents a single-chip 5-GHz fully integrated direct conversion transceiver for IEEE 802.11a WLAN systems, manufactured in 0.18-/spl mu/m CMOS. The IC features an innovative system architecture which takes advantage of the computing resources of the digital companion chip in order to eliminate I/Q mismatch and achieve accurately matched baseband filters. The integrated voltage-controlled oscillator and synthesizer achieve an integrated phase noise of less than 0.8/spl deg/ rms. The receiver has an overall noise figure of 5.2 dB and achieves sensitivity of -75 dBm at 54-Mb/s operation, both referred to the IC input. The transmit error vector magnitude is -33 dB at -5-dBm output power from the integrated power-amplifier driver amplifier. The transceiver occupies an area of 18.5 mm/sup 2/.

A 65 nm CMOS Multistandard, Multiband TV Tuner for Mobile and Multimedia Applications

This paper presents a direct conversion, multistandard TV tuner implemented on a 65 nm digital CMOS process occupying less than 7 . The tuner is compliant with several digital terrestrial, fixed and mobile TV standards, including DVB-T, DVB-H, T-DMB, and ISDB-T. It achieves a 3/3.2/3.5 dB noise figure at VHF, UHF, and L-band, respectively, while the measured sensitivity at UHF for the QPSK-frac12 DVB-T mode is at the PCB connector. The implemented RF front-ends support both single-ended and differential inputs. An integrated - fractional-N synthesizer operating from 1.2 to 1.8 GHz achieves less than 1 integrated phase error, thus enabling a maximum SNR in excess of 37 dB for VHF and UHF. Multistandard capability is also enabled by programmable channel-select filters. Power consumption is less than 140 mW in DVB-T mode for all three bands.

A digitally calibrated 5.15-5.825GHz transceiver for 802.11a wireless LANs in 0.18/spl mu/m CMOS

This transceiver achieves a transmit 1dB output compression point of +15dBm, and the overall receiver noise figure is 5dB. A power gain range of >45dB/65dB for transmit/receive and a PLL synthesizer frequency range of 4.9 to 5.85GHz with -79dBc/Hz phase noise at 10kHz offset have been measured. The IC is realized in 0.5/spl mu/m SiGe BICMOS technology and occupies 17mm/sup 2/.

A dual-band 5.15-5.35-GHz, 2.4-2.5-GHz 0.18-/spl mu/m CMOS transceiver for 802.11a/b/g wireless LAN

A single-chip dual-band 5.15-5.35-GHz and 2.4-2.5-GHz zero-IF transceiver for IEEE 802.11a/b/g WLAN systems is fabricated on a 0.18-/spl mu/m CMOS technology. It utilizes an innovative architecture including feedback paths that enable digital calibration to help eliminate analog circuit imperfections such as transmit and receive I/Q mismatch. The dual-band receive paths feature a 4.8-dB (3.5-dB) noise figure at 5.25 GHz (2.45 GHz). The corresponding sensitivity at 54 Mb/s operation is -76 dBm for 802.11a and -77 dBm for 802.11g, both referred at the input of the chip. The transmit chain achieves output 1-dB compression at 6 dBm (9 dBm) at 5 GHz (2.4 GHz) operation. Digital calibration helps achieve an error vector magnitude (EVM) of -33 dB (-31 dB) at 5 GHz (2.4 GHz) while transmitting -4 dBm at 54Mb/s. The die size is 19.3 mm/sup 2/ and the power consumption is 260 mW for the receiver and 320 mW (270 mW) for the transmitter at 5 GHz (2.4 GHz) operation.

20.2 A 16TX/16RX 60GHz 802.11ad chipset with single coaxial interface and polarization diversity

The IEEE 802.11ad standard supports PHY rates up to 6.7 Gbps on four 2 GHz-wide channels from 57 to 64 GHz. A 60 GHz system offers higher throughput than existing 802.11ac solutions but has several challenges for high-volume production including: integration in the host platform, automated test, and high link loss due to blockage and polarization mismatch. This paper presents a 802.11ad radio chipset capable of SC and OFDM modulation using a 16TX-16RX beamforming RF front-end, complete with an antenna array that supports polarization diversity. To aid low-cost integration in PC platforms, a single coaxial cable interface is used between chips. The chipset is capable of maintaining a link of 4.6 Gbps (PHY rate) at 10 m.

A 0.18/spl mu/m CMOS Dual-Band Direct-Conversion DVB-H Receiver

A 0.18mum CMOS direct-conversion dual-band DVB-H receiver occupies 9.7mm2 and achieves a 4dB/5dB NF at UHF/L-band, eliminating the need for an external LNA. By using a fractional-N synthesizer, the 470 to 890MHz and 1.4 to 1.8GHz bands are supported while achieving an integrated phase noise of <-41dBc. 6th-order LPF support channel bandwidths from 4 to 10 MHz. The overall power consumption is 295mW/280mW for continuous operation in the UHF/L-band, respectively

A 65nm CMOS multi-standard, multi-band mobile TV tuner

A direct conversion, 65 nm CMOS multi-standard TV tuner is presented, which is compliant with several digital terrestrial, fixed and mobile TV standards (DVB-T, DVB-H, T-DMB and ISDB-T, including 1-3 segment). The tuner achieves a 3/3/2.8 dB NF at VHF, UHF and L-band respectively, while consuming less than 140 mW in DVB-T mode. By using integrated transformers, both single-ended and differential RF inputs are supported. Multi-standard capability is enabled by programmable channel-select filters and a Sigma-Delta fractional-N synthesizer.

CMOS tuners for mobile TV

Digital video reception is emerging as the latest feature toward multimedia-enriched handheld devices. Mobile battery-operated devices require small-size tuners that consume low power and are amenable to single-chip integration with the baseband demodulator. Following an overview of the system and circuit-level implementation challenges of mobile TV standards such as DVB-H and T-DMB, this article presents a dual-band direct conversion tuner for DVB-H. Architecture and circuit trade-offs are discussed, and detailed measurements are presented. The tuner occupies 9.7 mm2 and achieves a 4 dB NF at both UHF and L-band, eliminating the need for an external LNA. By using a fractional-TV synthesizer both 470-890 MHz and 1.4-1.8 GHz bands are supported, while achieving an integrated phase noise of less than -41 dBc. Sixth-order low-pass filters support channel bandwidths from 4 to 10 MHz

A single-chip, 5.15GHz-5.35GHz, 2.4GHz-2.5GHz, 0.18/spl mu/m CMOS RF transceiver for 802.11a/b/g wireless LAN

A dual band, 5.15GHz-5.35GHz, 2.4GHz-2.5GHz, zero-IF transceiver is fabricated on a 0.18/spl mu/m CMOS process. The fully integrated synthesizer and VCO achieve an integrated phase error of 0.8/spl deg/ at 5GHz. The transmitter achieves -33dB EVM, while the receiver features a 5.2dB noise figure (NF) at 5.25GHz and 3.5dB NF at 2.45GHz. An architecture including feedback paths enables digital calibration, which help eliminate I/Q mismatch and achieve accurately matched baseband filter tuning.

A dual-band 4.9-5.95 GHz, 2.3-2.5 GHz, 0.18 /spl mu/m CMOS transceiver for 802.11 a/b/g-802.16d/e

A zero-IF, 4.9-5.95 GHz, 2.3-2.5 GHz, transceiver is fabricated on a 0.18 /spl mu/m CMOS process. By using a fractional-N synthesizer, an integrated phase error of 0.6/spl deg/ (0.7/spl deg/) at 5 GHz (2.4 GHz) is achieved, while supporting fine frequency resolution. Digital calibration eliminates I/Q mismatch and achieves accurately matched baseband filters. The transceiver is compliant to 802.11a/b/g, while programmable bandwidth filters and an EVM of -35 dB in both transmit and receive, make it suitable for applications based on 802.16d/e.