Ibrahim M. Abdel-Motaleb

A GUMMEL-POON MODEL FOR ABRUPT AND GRADED HETEROJUNCTION BIPOLAR TRANSISTORS (HBTS)

Abstract A Gummel-Poon model for abrupt and graded GaAlAs/GaAs/GaAs heterojunction bipolar transistors (HBTs) is developed. The effect of carrier recombination at the emitter-base heterojunction, space charge region (SCR) width modulation effect, and base-widening effect at large collector currents have been considered. Results from this model are compared with numerical results, experimental results, and results from the most recent analytical models. The results show that the common-emitter current gain behavior in the low collector current region can be predicted more accurately by this model, and that interface and surface recombination affect the current gain more dominantly than the other recombination processes. Dependence of cutoff frequency on collector current obtained from the present model agrees well with the experimental results. This model can also predict both current gain and cutoff frequency falloffs at large collector current. This model can be easily implemented in the SPICE program.

An analytical model for current-voltage characteristics of quantum-well heterojunction field-effect transistors

Abstract An analytical model has been developed for Insulated-Gate Inverted-Structure High Electron Mobility Transistors (I 2 -HEMTs) and Double Heterojunction High Electron Mobility Transistors (DH-HEMTs). In this model, the quasi-triangular potential well approximation is used to calculate the top-heterojunction Fermi potential as a function of the 2DEG concentration inside the quantum-well. A closed-form charge control formula has been derived. The 2DEG concentration vs gate voltage obtained from this model is found to agree with the self-consistent numerical model. Based on this charge-control model, the current-voltage relationships for I 2 -HEMTs and DH-HEMTs are obtained. In these relationships, the buffer 2DEG channel conduction beneath the quantum well and cross linking current inside the quantum well are considered. This model is compared with the experimental results and found to be fairly accurate.

An analytical all-injection charge-based model for graded-base HBTs

Abstract Current transpsort and charge concentration in graded base heterojunction bipolar transistors (HBTs) have been investigated, and an all injection charge-based model suitable for implementation in computer aided design tools has been developed. In this model, injected current, charge and recombination current components are formulated for all levels of injection. Base grading effect on current components, current gain and cutoff frequency in the high current regions are studied. This model is a general model which is also valid for modeling ungraded base HBTs. The model is found to be in good agreement with the experimental and numerical results.

Small-signal non-quasi-static model for single and double heterojunction bipolar transistors

Abstract A large-signal nonquasi-static model for heterojunction bipolar transistors (HBTs) is presented. Using this model, the turn-on and turn-off transient characteristics were simulated. The simulation results obtained using this model and that of Gummel-Poon model are compared with the results obtained numerically. This comparison shows that our model can more accurately predict the device transient performance. The model accuracy can be improved even further if nonquasi-static junction capacitance models are used. Using our model, it will be possible to simulate digital circuits in the gigabit range.

Modeling of junction capacitances of graded base heterojunction bipolar transistors

Abstract Capacitance models for emitter-base and collector-base junctions of graded base heterojunction bipolar transistors (HBTs) are developed. Effects of base grading on potential barriers, space-charge region (SCR) boundaries, and emitter-base and collector-base junction capacitances are investigated. The emitter-base capacitance is divided into depletion capacitance and capacitance resulting from the mobile carriers in the SCR. To obtain a closed-form solution for the capacitance, intrinsic potential is assumed to be piecewise linear. For the collector-base capacitance, depletion approximation is employed, since the junction is usually reverse-biased in normal operation. It is demonstrated that the present model is quite consistent with the measured data.

An analytical charge control model for AlGaAs modulation‐doped field effect transistors

An analytical charge control model for AlGaAs modulation‐doped field effect transistors has been developed. The model has two regions: the linear, represented by a linear correspondence, and the saturation, represented by an exponential function. Using two fitting parameters, the slope of the linear curve is modified to reduce the subthreshold current and to determine the point separating the linear and saturation regions. Using this model, the device performance can be predicted to a very high degree of accuracy, since the charge‐voltage relation has been accurately modeled using parameters related to device characteristics and dimensions. A dc model for the device current‐voltage (I‐V) characteristics has been developed. The parasitic current which may flow through the doped layer of the channel has been considered. The velocity saturation of the charges has been accounted for, and the saturation drain‐source voltage has been accurately determined. This model can provide accuracy without sacrificing sim...

Nonlinear model for MODFET parasitic resistances

Abstract An analytical nonlinear model for the parasitic resistances of modulation doped field effect transistors (MODFETs) has been developed. In this model, the effect of electron velocity saturation, surface potential and gate voltage on the nonlinearity of the resistances is investigated. The MODFET I – V characteristics obtained when this nonlinear parasitic model is used are found to be in a good agreement with the experimental data. This study shows that this model can be valid for all common MODFET structures. The study shows also that using this model may be essential for achieving accurate noise figure evaluation and small and large signal analysis simulation, for high-power devices. Because the model is simple, it can be easily implemented in a circuit simulator such as SPICE.

Estimation of the 2DEG layer location in quantum-well structures

Abstract Simple analytical relations for the average two-dimensional electron gas (2DEG) distance from the top heterointerface and the average effective spread of the 2DEG have been developed for double-heterojunction high electron mobility transistors (DH-HEMTs). In this model, the triangular well approximation is employed.

Analysis of the switching characteristics of NMOS common drain FET logic (CDFL)

The switching characteristics of a novel NMOS structure, the common drain FET logic (CDFL) is studied. A technique utilizing a load capacitor charging and discharging mechanism to calculate the output waveform of NMOS CDFL buffer and DCFL (direct coupled FET logic) inverter has been used. The results show that a CDFL buffer can be at least twice as fast as a DCFL inverter occupying the same area. Using the buffer to build positive logic gates and the inverter to build negative logic gates leads to at least at 100% increase in the speed of the overall circuit and a 33% decrease in the occupied area.<<ETX>>

Analysis of latch-up in GaAs complementary logic structures

GaAs complementary FET logic structures have n/sup +/ and p/sup +/ doped areas separated by areas of semi-insulating (SI) GaAs. Such doped patterns form stray p-i-n double injection diodes which may cause latch-up. Using a SPICE equivalent circuit for the latch-up diodes, the effect of latch-up on the performance of the logic gates has been simulated. This study shows that latch-up can severely affect the performance of the logic gates, and that the distance between the injecting contacts, background concentration of the SI material, and temperature are critical parameters in latch-up susceptibility.<<ETX>>