Ibrahim M. Elfadel

A block rational Arnoldi algorithm for multipoint passive model-order reduction of multiport RLC networks

Work in the area of model-order reduction for RLC interconnect networks has focused on building reduced-order models that preserve the circuit-theoretic properties of the network, such as stability, passivity, and synthesizability (Silveira et al., 1996). Passivity is the one circuit-theoretic property that is vital for the successful simulation of a large circuit netlist containing reduced-order models of its interconnect networks. Non-passive reduced-order models may lead to instabilities even if they are themselves stable. We address the problem of guaranteeing the accuracy and passivity of reduced-order models of multiport RLC networks at any finite number of expansion points. The novel passivity-preserving model-order reduction scheme is a block version of the rational Arnoldi algorithm (Ruhe, 1994). The scheme reduces to that of (Odabasioglu et al., 1997) when applied to a single expansion point at zero frequency. Although the treatment of this paper is restricted to expansion points that are on the negative real axis, it is shown that the resulting passive reduced-order model is superior in accuracy to the one that would result from expanding the original model around a single point. Nyquist plots are used to illustrate both the passivity and the accuracy of the reduced order models.

Transient analysis of lossy transmission lines: an efficient approach based on the method of Characteristics

This paper is devoted to transient analysis of lossy transmission lines characterized by frequency-dependent parameters. A public dataset of parameters for three line examples (a module, a board, and a cable) is used, and a new example of on-chip interconnect is introduced. This dataset provides a well established and realistic benchmark for accuracy and timing analysis of interconnect analysis tools. Particular attention is devoted to the intrinsic consistency and causality of these parameters. Several implementations based on generalizations of the well-known method-of-characteristics are presented. The key feature of such techniques is the extraction of the line modal delays. Therefore, the method is highly optimized for long interconnects characterized by significant propagation delay. Nonetheless, the method is also successfully applied here to a short high/loss on-chip line, for which other approaches based on lumped matrix rational approximations can also be used with high efficiency. This paper shows that the efficiency of delay extraction techniques is strongly dependent on the particular circuit implementation and several practical issues including generation of rational approximations and time step control are discussed in detail.

Gradient-based optimization of custom circuits using a static-timing formulation

This paper describes a method of optimally sizing digital circuits on a static-timing basis. All paths through the logic are considered simultaneously and no input patterns need be specified by the user. The method is unique in that it is based on gradient-based, nonlinear optimization and can accommodate transistor-level schematics without the need for pre-characterization. It employs efficient time-domain simulation and gradient computation for each channel-connected component. A large-scale, general-purpose, nonlinear optimization package is used to solve the tuning problem. A prototype tuner has been developed that accommodates combinational circuits consisting of parameterized library cells. Numerical results are presented.

A comparative study of two transient analysis algorithms for lossy transmission lines with frequency-dependent data

Two general algorithms for the modeling of lossy transmission lines with frequency-dependent parameters are contrasted and compared. The first is based on the generalized method of characteristics while the second is based on the more recent Pade macromodeling approach. The different approximations made in these two algorithms are contrasted and computational evidence is presented to show that these two methods complement rather than compete with each other.

Stochastic Testing Method for Transistor-Level Uncertainty Quantification Based on Generalized Polynomial Chaos

Uncertainties have become a major concern in integrated circuit design. In order to avoid the huge number of repeated simulations in conventional Monte Carlo flows, this paper presents an intrusive spectral simulator for statistical circuit analysis. Our simulator employs the recently developed generalized polynomial chaos expansion to perform uncertainty quantification of nonlinear transistor circuits with both Gaussian and non-Gaussian random parameters. We modify the nonintrusive stochastic collocation (SC) method and develop an intrusive variant called stochastic testing (ST) method. Compared with the popular intrusive stochastic Galerkin (SG) method, the coupled deterministic equations resulting from our proposed ST method can be solved in a decoupled manner at each time point. At the same time, ST requires fewer samples and allows more flexible time step size controls than directly using a nonintrusive SC solver. These two properties make ST more efficient than SG and than existing SC methods, and more suitable for time-domain circuit simulation. Simulation results of several digital, analog and RF circuits are reported. Since our algorithm is based on generic mathematical models, the proposed ST algorithm can be applied to many other engineering problems.

A capacitance solver for incremental variation-aware extraction

Lithographic limitations and manufacturing uncertainties are resulting in fabricated shapes on wafer that are topologically equivalent, but geometrically different from the corresponding drawn shapes. While first-order sensitivity information can measure the change in pattern parasitics when the shape variations are small, there is still a need for a high-order algorithm that can extract parasitic variations incrementally in the presence of a large number of simultaneous shape variations. This paper proposes such an algorithm based on the well-known method of floating random walk (FRW). Specifically, we formalize the notion of random path sharing between several conductors undergoing shape perturbations and use it as a basis of a fast capacitance sensitivity extraction algorithm and a fast incremental variational capacitance extraction algorithm. The efficiency of these algorithms is further improved with a novel FRW method for dealing with layered media. Our numerical examples show a 10X speed up with respect to the boundary-element method adjoint or finite-difference sensitivity extraction, and more than 560X speed up with respect to a non-incremental FRW method for a high-order variational extraction.

Zeros and passivity of Arnoldi-reduced-order models for interconnect networks

CAD tools and research in the area of reduced-ordermodeling of large linear interconnect networks have evolvedfrom merely finding a Pad´ e approximation for the givennetwork transfer function to finding an approximate transferfunction that preserves such circuit-theoretic propertiesof the network as stability, passivity, and RLC synthesizability.In particular, preserving passivity guarantees thatthe reduced-order models will be well-behaved when embeddedback in the circuit where the interconnect networkoriginated. While stability can be ascertained by studyingthe poles of the reduced-order transfer function, passivitydepends on both the poles and zeros of the networkdriving-point impedance. In this paper, we present a novelmethod for studying the zeros of reduced-order transferfunctions and show how it yields conclusions about passivityand synthesizability. Moreover, in order to obtain aguaranteed-passive reduced-order model for multiport RCnetworks, a new algorithm based on the Arnoldi iteration ispresented. This algorithm is as computationallyefficient asthe one used to generate guaranteed-stable reduced-ordermodels [Coordinate-transformed Arnoldi for generating guranteed stable reduced-order models for RLC circuits].

A hierarchical floating random walk algorithm for fabric-aware 3D capacitance extraction

With the adoption of ultra regular fabric paradigms for controlling design printability at the 22 nm node and beyond, there is an emerging need for a layout-driven, pattern-based parasitic extraction of alternative fabric layouts. In this paper, we propose a hierarchical floating random walk (HFRW) algorithm for computing the 3D capacitances of a large number of topologically different layout configurations that are all composed of the same layout motifs. Our algorithm is not a standard hierarchical domain decomposition extension of the well established floating random walk technique, but rather a novel algorithm that employs Markov Transition Matrices. Specifically, unlike the fast-multipole boundary element method and hierarchical domain decomposition (which use a far-field approximation to gain computational efficiency), our proposed algorithm is exact and does not rely on any tradeoff between accuracy and computational efficiency. Instead, it relies on a tradeoff between memory and computational efficiency. Since floating random walk type of algorithms have generally minimal memory requirements, such a tradeoff does not result in any practical limitations. The main practical advantage of the proposed algorithm is its ability to handle a set of layout configurations in a complexity that is basically independent of the set size. For instance, in a large 3D layout example, the capacitance calculation of 120 different configurations made of similar motifs is accomplished in the time required to solve independently just 2 configurations, i.e. a 60× speedup.

Efficient Uncertainty Quantification for the Periodic Steady State of Forced and Autonomous Circuits

This brief proposes an uncertainty quantification method for the periodic steady-state (PSS) analysis with both Gaussian and non-Gaussian variations. Our stochastic testing formulation for the PSS problem provides superior efficiency over both Monte Carlo methods and existing spectral methods. The numerical implementation of a stochastic shooting Newton solver is presented for both forced and autonomous circuits. Simulation results on some analog/RF circuits are reported to show the effectiveness of our proposed algorithms.

Stochastic testing simulator for integrated circuits and MEMS: Hierarchical and sparse techniques

Process variations are a major concern in todays chip design since they can significantly degrade chip performance. To predict such degradation, existing circuit and MEMS simulators rely on Monte Carlo algorithms, which are typically too slow. Therefore, novel fast stochastic simulators are highly desired. This paper first reviews our recently developed stochastic testing simulator that can achieve speedup factors of hundreds to thousands over Monte Carlo. Then, we develop a fast hierarchical stochastic spectral simulator to simulate a complex circuit or system consisting of several blocks. We further present a fast simulation approach based on anchored ANOVA (analysis of variance) for some design problems with many process variations. This approach can reduce the simulation cost and can identify which variation sources have strong impacts on the circuits performance. The simulation results of some circuit and MEMS examples are reported to show the effectiveness of our simulator.