Ichiro Okabayashi

Processing element design for a parallel computer

A study has been made of how cost-effectiveness due to the improvement of VLSI technology can apply to a scientific computer system without performance loss. The result is a parallel computer, ADENA (Alternating Direction Edition Nexus Array), with a core consisting of four kinds of VLSI chips, two for processor elements (PES) and two for the interprocessor network (plus some memory chips). An overview of ADENA and an analysis of its performance are given. The design considerations for the PEs incorporated in ADENA are discussed. The factors that limit performance in a parallel processing environment are analyzed, and the measures employed to improve these factors at the LSI design level are described. The 42.6 sq cm CMOS PEs reach a peak performance of 20 MFLOPS and a 256-PE ADENA 1.5 GFLOPS has been achieved and 300 to 400 MFLOPS for PDE applications.<<ETX>>

Parallel computer ADENART—its architecture and application

A new parallel computer, ADENART (previously it was called ADENA,) for numerical applications has been developed. It is composed of 256 processing elements (:PEs) and interconnection networtcHXnet.) Each PE consists of a dedicated floating-point processor VLSI whose sustained performance is 10 MFLOPS, a communication controller VLSI and locally-distributed memories. The peak performance of the system is, therefore, 2.56GFLOPS. HXnet supports two types of efficient data-transfer modes; FAST mode and SLOW mode. Both of them are useful for various applications. The practical performance of ADENART system has been evaluated by several application programs. In partial differential equation solver, the system performance was measured as 475 MFLOPS.

A proposed structure of a 4 Mbit content-addressable and sorting memory

A new structure for a high-density 4-Mb CAM (content addressable memory) with sorting function (sort-CAM) is proposed. Retrieval or sorting operations are done in word-parallel/bit-serial manner at the device. This is different from previous CAMs where operations are done in word-parallel/bit-parallel or flash manner. The device organization, circuits for retrieval or sorting, and chip operations are explained. Estimated performance of the device and chip size are also discussed. The device has 64 K-word&times;64-b organization and a 3.1-MB/s sorting speed. In practical applications, such as RDB (relational database) systems, this speed is enough, but a number of chips should be connected if larger data volume is needed

Chapter generation for digital video recorder based on perceptual clustering

We propose a novel automatic chapter generating technique for digital video recorder (DVR) based on a perceptual clustering. Clustering with two-staged hierarchy is introduced for the first time, showing better performance than previous approaches without requiring any rule-based processes like recognition or modeling. Implementation into our DVR is planned.