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Dive into the research topics where Ikechi Augustine Ukaegbu is active.

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Featured researches published by Ikechi Augustine Ukaegbu.


Journal of The Optical Society of Korea | 2013

10 Gbps Transimpedance Amplifier-Receiver for Optical Interconnects

Jamshid Sangirov; Ikechi Augustine Ukaegbu; Tae-Woo Lee; Mu Hee Cho; Hyo-Hoon Park

2with power consumption of 16.9 mW at 1.3 V. The measured input-referred noise of optical TIA-Rx is 20 pA/√Hz with a 3-dB bandwidth of 6.9 GHz. The proposed TIA-Rx achieved a high gain-bandwidth product per DC power figure of merit of 408 GHzΩ /mW.


Optics Express | 2014

40 Gb/s optical subassembly module for a multi-channel bidirectional optical link

Jamshid Sangirov; Gwan-Chong Joo; Jae-Shik Choi; Do-Hoon Kim; Byueng-Su Yoo; Ikechi Augustine Ukaegbu; Nguyen T. H. Nga; Jong-Hun Kim; Tae-Woo Lee; Mu Hee Cho; Hyo-Hoon Park

A 40 Gb/s bidirectional optical link using four-channel optical subassembly (OSA) modules and two different wavelengths for the up- and down-link is demonstrated. Widely separated wavelengths of 850 nm and 1060 nm are used to reduce the optical crosstalk between the up- and down-link signals. Due to the integration capabilities of silicon, the OSA is implemented, all based on silicon: V-grooved silicon substrates to embed fibers and silicon optical benches (SiOBs) to mount optical components. The SiOBs are separately prepared for array chips of photodiodes (PDs), vertical-cavity surface-emitting lasers (VCSELs), and monitoring PDs, which are serially configured on an optical fiber array for direct coupling to the transmission fibers. The separation of the up- and down-link wavelengths is implemented using a wavelength-filtering 45° mirror which is formed in the fiber under the VCSEL. To guide the light signal to the PD another 45° mirror is formed at the end of the fiber. The fabricated bidirectional OSA module shows good performances with a clear eye-diagram and a BER of less than 10(-12) at a data rate of 10 Gb/s for each of the channels with input powers of -8 dBm and -6.5 dBm for the up-link and the down-link, respectively. The measured inter-channel crosstalk of the bidirectional 40 Gb/s optical link is about -22.6 dB, while the full-duplex operation mode demonstrates negligible crosstalk between the up- and down-link.


international conference on advanced communication technology | 2014

Design of small-area transimpedance optical receiver module for optical interconnects

Jamshid Sangirov; Ikechi Augustine Ukaegbu; Nga T. H. Nguyen; Tae-Woo Lee; Mu-Hee Cho; Hyo-Hoon Park

The development and miniaturization of electronic devices and components is pushing the system devices and their interconnecting interfaces to become even smaller. Thus, reducing the size of receiver (Rx) and transmitter (Tx) chips plays an plays an important role in designing a small-size optical modules utilized in o/e and e/o converters. Therefore, designing a small-area optical Rx may require intuitive solutions, such as building single-ended Rx and utilizing some of the advantages of differential Rx. Optical Rx should convert optical input signal to voltage output signal and provide sufficient gain and frequency operation for feeding to subsequent blocks including clock and data recovery circuit (CDR) and/or Serializer and Deserializer (SerDes). Therefore, we have designed a small-area transimpedance optical receiver (TIORx) using regulated-cascode (RGC) as an input stage which converts input photocurrent to voltage signal. The RGC block is connected to post amplifying stages to increase the overall transimpedance gain of the TIORx. The post amplifying gain stages utilizes two intersecting active feedback in order to increase the frequency operation in addition to increasing the gain of the proposed TIORx chip. The TIORx module is designed in a 0.13μm CMOS technology and works up to 10 Gbps data rate. The TIORx chip core occupies an area of 0.051mm2 with power consumption of 16.9 mW at 1.3 V. A measured 3-dB bandwidth of 6.9 GHz was obtained for the TIORx module with a transimpedance gain of 60 dBQ.


IEEE Photonics Technology Letters | 2009

Bidirectional CMOS Transceiver With Automatic Mode Control for Chip-to-Chip Optical Interconnects

Trong-Hieu Ngo; Nga T. H. Nguyen; Ikechi Augustine Ukaegbu; Tae-Woo Lee; Hyo-Hoon Park

A bidirectional transceiver (Bi-TRx) integrated with a novel transmission envelope detector, which can detect the presence of received signals to generate a mode control signal automatically, is proposed in this letter. Implemented in a 0.18-mum complementary metal-oxide-semiconductor technology, the Bi-TRx occupies an area of 1.08 mm2 , and dissipates 42 and 49 mW in transmitter (Tx) and receiver (Rx) modes, respectively. It achieves a 3-dB bandwidth of 4.4 and 4 GHz in Tx and Rx modes, respectively, while the disabled outputs for the Tx and Rx modes are isolated with 41 and 68 dB, respectively, from the enabled outputs.


Optical Engineering | 2011

Analytical model for crosstalk analysis of optoelectronic transmitter modules for optical interconnects

Ikechi Augustine Ukaegbu; Jamshid Sangirov; Mu Hee Cho; Tae-Woo Lee; Hyo-Hoon Park

In this paper, a crosstalk expression and equivalent circuit model have been proposed based on RLC line model and interconnect parameters for wire-bonded and flip-chip bonded multichannel optoelectronic modules. The analytical expression and model are accurate for computing crosstalk of interconnects used in chip packaging. In addition, full-wave simulation and experimental results from total crosstalk measurement are discussed.


opto-electronics and communications conference | 2012

Short turn-on/off time linear voltage regulator with data detector for power-aware optical interconnect system

Jamshid Sangirov; Ikechi Augustine Ukaegbu; Tae-Woo Lee; Mu-Hee Cho; Hyo-Hoon Park

A proposed power-aware optical interconnection system consists of a supply control voltage regulator, a receiver circuit, and a transmitter circuit. The supply control voltage regulator power consumption is 220 μA at 3.3 V and the optical receiver and transmitter has 27 mA and 64 mA at 1.8 V respectively. The transient response of supply control voltage regulator has 3.1 ns and 0.4 ns for rising and falling time, respectively.


Proceedings of SPIE | 2011

Low-power and high-speed SerDes with new dynamic latch and flip-flop for optical interconnect in 180 nm CMOS technology

Jamshid Sangirov; Ikechi Augustine Ukaegbu; Tae-Woo Lee; Mu Hee Cho; Hyo-Hoon Park

We propose a new dynamic D-latch for low-power high-speed SerDes in chip-to-chip optical interconnect. The overall SerDes circuit uses 3.6 times less number of transistors, with smaller SerDes occupying 50% less area, compared to the previous works. The SerDes operates up to 10 Gbps data rate, and the power consumption is 49.3 mW at 1.8 V, which is 30 % less power.


IEEE Photonics Technology Letters | 2011

2.5-Gb/s/ch Long Wavelength Transmitter Modules for Chip-to-Chip Optical PCB Applications

Ikechi Augustine Ukaegbu; Do-Won Kim; Mu Hee Cho; Tae-Woo Lee; Hyo-Hoon Park

We have fabricated 2.5-Gb/s/ch long wavelength optical transmitter modules in planar and multichip module structures for chip-to-chip optical printed-circuit board (OPCB) applications. Their performance has been analyzed and compared with two types of short wavelength structures. The long wavelength multichip module showed a 3-dB bandwidth of 2.46 GHz while the planar showed 2.16 GHz. The modules showed clear eye openings at 2.5 Gb/s with a bit-error rate less than 10-12 and can be used for optical interconnections in OPCBs.


international conference on optical internet | 2010

Crosstalk analysis of planar and multi-chip transmitter modules for optical PCB applications

Ikechi Augustine Ukaegbu; Mu Hee Cho; Tae-Woo Lee; Hyo-Hoon Park

As the speed of integrated circuits increases, inductive coupling becomes an issue for the packaging interconnect technologies. Two transmitter modules (planar and multichip) have been fabricated for crosstalk analysis. The modules are prepared using 1×4 VCSELs and driver integrated circuit (IC) fabricated in a 0.18 µm Si-CMOS technology. The planar module has been fabricated using the conventional wire-bonding technology for interconnect between the vertical cavity surface emitting laser (VCSEL) and the driver chip while the multichip module has been prepared using flip-chip bonding process. The modules showed clear eye openings at 2.5 Gb/s with bit error rate less than 10−12. This work focuses on the crosstalk effect due to the electrical interconnects between the driver chip and VCSEL chip. Crosstalk improvement of the multichip module over the planar module is shown analytically and by field simulation. Equivalent circuit model of the interconnects has been extracted based on RLC line model.


Journal of Circuits, Systems, and Computers | 2015

Power Saving Rx Design for Optical Modules

Jamshid Sangirov; Ikechi Augustine Ukaegbu; Nga T. H. Nguyen; Tae-Woo Lee; Mu Hee Cho; Hyo-Hoon Park

In this paper, a power saving optical receiver (Rx) module has been designed, fabricated using a 0.13-μm CMOS technology and demonstrated the performance with experimental results. In the Rx module, a power control block is designed to control the power of Rx according to the presence or absence of an incoming signal at the input of Rx. The Rx switches to a passive operation mode when there is no signal at Rx input. In the passive operation mode, the fabricated Rx shows a power saving efficiency of about 51%, where Rx is not receiving. When there is an input signal at Rx input, the Rx switches to an active operation mode with a system efficiency of about 97.5%. The experimental data shows that the Rx module consumes of about 67 mW at 1.3 V and power control block consumes of about 1.6 mW at 1.4 V. The measured 3-dB bandwidth of 2.56 GHz was recorded for optical Rx module. The bit error rate (BER) performance of 10−12 is achieved for the proposed optical Rx module up to 2.5 Gbps data rate with a clear eye-diagram by a very low optical input power of about −3 dBm.

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Tae-Woo Lee

Seoul National University

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Gulomjon Sangirov

Harbin Engineering University

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Kwang-Seong Choi

Electronics and Telecommunications Research Institute

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