Ilhoon Shin

Hot/cold clustering for page mapping in NAND flash memory

NAND flash memory, which is widely used as a storage medium for mobile devices because of its lightweight, shock-resistant, silent, and energy-efficient characteristics, lacks an over-write operation. Therefore, NAND-based storage devices deploy a flash translation layer (FTL) to emulate the over-write operation with out-of-place updates. However, as out-of-place updates write data to new unwritten spaces, clean spaces eventually become scarce. This initiates a garbage collection process that accompanies several NAND writes and erases. Thus, it is important to reduce the latency and frequency of garbage collection, which is a primary aim of the present work. The central idea is to cluster hot and cold data separately to reduce the number of valid pages in a victim block at the time of garbage collection. Reducing the number of valid pages of the victim block contributes to the reduction of both the latency and frequency of the garbage collection process. Trace-driven simulations show that the proposed hot/cold clustering improves write throughput by up to 18%.

Reducing computational overhead of flash translation layer with hashed page tables

NAND flash memory is lightweight, small, shock-resistant, silent, and low in energy consumption. Thus it is widely used as a storage medium of various block devices such as SD cards, USB drives, and more recently, solid-state drives. However, given that it does not support the overwrite function, NAND-based block devices embed a firmware called Flash Translation Layer (FTL) to emulate the block device interface. The performance of a NAND-based block device is mainly determined by the efficiency of FTL as well as the performance of the NAND flash memory itself. Most previous work focused on, and succeeded in, significantly reducing the number of NAND operations such as write and erase. However, the overall performance was not substantially improved because of the enormous computational overhead of operating FTL. The overhead mainly stems from a linear search of target sectors for the entire log block space. This work presents a method to reduce the number of linear searches with the help of a hashed page table. A trace-driven simulation shows that the hashed page table effectively reduces the computational overhead of the existing scheme. The total elapsed time decreases by up to 46% compared to the original FAST scheme, and the impact of the CPU frequency on the performance of NAND-based block devices is also reduced. The hashed page table is anticipated to make FAST-like schemes feasible for NAND-based block devices which embed low-speed controllers.

Double Hot/Cold Clustering for Solid State Drives

Solid State Drives (SSDs) which connect NAND-flash memory in parallel is going to replace Hard Disk Drives (HDDs). The physical trait of SSD is different from HDD and it uses Flash Translation Layer (FTL) to emulate HDD. Garbage Collection is the process of making an available sphere in SSD which has no function of an over-write. In the case of general policy of FTL, both of valid and invalid pages are randomly mixed, but if it could be separated, an effect of Garbage Collection can be improved. This paper presents a double hot/cold clustering scheme that separates the frequently overwritten region from the opposite. The performance evaluation result shows that the improvement is between 44.3% in maximum and 3.9% in minimum.

Demand-based flash translation layer considering spatial locality

A flash translation layer (FTL) is a firmware inside a SSD to support traditional file systems with NAND flash memory. One such FTL, the page mapping scheme shows high performance but requires a large mapping table to be stored in random access memory (RAM). Demand-based FTL (DFTL), which only stores frequently used mapping entries in RAM, overcomes this drawback. However, it has a weakness that the cached mapping table (CMT) that contains frequently used mapping entries must be sequentially searched; moreover, if the CMT is kept too small, frequent replacement of mapping entries may impair performance. Here, we propose a scheme in which the spatial locality of typical disk patterns is employed and clustered mapping entries are loaded into RAM. The scanning overhead of the CMT is also eliminated by using two-level mapping tables. We experimentally show that the presented scheme significantly reduces RAM usage while retaining comparable performance.

Implementing secure file deletion in NANDbased block devices with internal buffers

The goal of this work is to support secure file deletion in NAND-based block devices with an internal buffer. Existing secure file deletion tools for hard disks overwrite the file contents many times, causing them to become distorted and irrecoverable. However, NAND-based block devices perform an out-of-place update on the overwrite request, meaning that the original data are preserved without modification and restorable. Furthermore, if there is an internal buffer, then this absorbs the overwrite request. Thus, the existing secure file deletion tools do not work properly in NAND-based block devices. In order to support secure file deletion, this work presents a modification of the internal buffer manager and the underlying flash translation layer. The buffer manager records the overwrite count of each logical page, and sends a request to permanently erase the secure data when the overwrite count exceeds a threshold. Upon receiving this request, the flash translation layer erases all of the old data on the target logical page. The performance overhead resulting from this secure file deletion is evaluated by a trace-driven simulation of representative flash translation layer schemes. The results show that the page mapping method delivers the best performance of the representative flash translation layer schemes, in spite of suffering significant performance degradation.

Active log pool for fully associative sector translation

Although NAND-based block devices offer good average performance compared to hard disk drives, their poor worst-case performance can be a serious problem in servers and real-time systems. In order to address it, this study proposes to use an active log pool to isolate the working sectors of each process to different NAND blocks. Doing so reduces the association degree of log blocks, which in turn reduces the worst-case write latency. A trace-driven simulation shows that the worst-case latency is reduced up to 1/9 compared to the original scheme without hurting the average performance severely.

Evaluating the Worst-Case Performance of Flash Translation Layer

NAND-based block devices are widely used in various computing devices, and the intesive studies have been performed to improve the average performance of NAND-based block devices with desiging efficient flash translation layer (FTL) schemes. However, the worst-case performance has been beyond the focus. The goal of this work is to evaluate the worst-case performance of the representive FTL schemes. The trace-drive simulation shows that the page mapping scheme delivers the best worst-case performance. In contrast, the FAST scheme and the SBAST scheme, which deliver a good average performance, are bad in the aspect of the worst-case performance.

HA-SBAST: History-Based Flash Translation Layer for NAND Flash Memory

NAND flash memory does not support the over-write operation and NAND-based storages need to deploy flash translation layer (FTL) that emulates the standard block device interface. The main function of FTL is to perform the out-of-place update and to maintain the mapping information between the logical sector numbers and their physical locations. The aim of the work is to present the efficient FTL sector mapping scheme for resource harsh embedded systems. The prime idea is to induce the low-cost sequential merge by allocating the dedicated write buffer for the sequential block. The random blocks share the write buffer to utilize the buffer space as possible. The sequentiality of blocks is evaluated with the past write pattern. The trace-driven simulation shows that the proposed scheme improves the overall performance of NAND-based storage up to 18.6 % compared to the FTL scheme that does not induce the sequential merge.

Dynamic active log pool for improving worst-case performance of memory cards

Severe performance fluctuations and thus low worst-case performance are serious problems for NAND-based memory cards used as storage devices in portable consumer electronics. These problems are mainly caused by the erasebefore- write restriction of NAND flash memory. As the write to NAND is accumulated, a garbage collection is performed to reproduce clean blocks. The execution time of the garbage collection greatly depends on the association degree of the NAND blocks selected as victim. In other words, if the victim block has the high association degree, the execution time of the garbage collection becomes long, which adversely affects the overall performance of the memory card. To address this problem, this paper proposes a new hybrid mapping flash translation layer policy using dynamic active log pool, partial merge, and moving valid pages that reduce the association degree of victim blocks. The results of a trace-driven simulation show that the proposed policy reduces the worst-case latency of write requests by up to 44.8% compared to the best alternative policy. The average latency is also shortened by up to 4.1%.

Fire prevention in gas stove with gas sensors

This paper presents to use gas sensors to implement a safer home from a fire caused by the gas stove. Nowadays, the ratio of the families that consist of one person or old people only is increasing and thus the probability of the fire caused by forgetting turning off the gas stove is also increasing. In order to prevent this kind of fire, the presented appliance detects the poisonous gases generated on burning of pots or food, and it closes the gas valve automatically using a motor on the detection of the emergent situation. We implement the presented idea to the prototype appliance and prove the correctness of its function.