Ilias Chlis

Analyses and techniques for phase noise reduction in CMOS Colpitts oscillator topology

Summary This paper reports the analyses of three techniques for phase noise reduction in the complementary metal-oxide semiconductor (CMOS) Colpitts oscillator circuit topology. Namely, the three techniques are inductive degeneration, noise filter, and optimum current density. The design of the circuit topology is carried out in 28-nm bulk CMOS technology. The analytical expression of the oscillation frequency is derived and validated through circuit simulations. Moreover, the theoretical analyses of the three techniques are carried out and verified by means of circuit simulations within a commercial design environment. The results obtained for the inductive degeneration and noise filter show the existence of an optimum inductance for minimum phase noise. The results obtained for the optimum bias current density technique applied to a Colpitts oscillator circuit topology incorporating either inductive degeneration or noise filter show the existence of an optimum bias current density for minimum phase noise. Overall, the analyses show that the adoption of these techniques may lead to a potential phase noise reduction up to 19 dB at a 1-MHz frequency offset for an oscillation frequency of 10 GHz.

Analysis of Phase Noise in 28 nm CMOS LC Oscillator Differential Topologies: Armstrong, Colpitts, Hartley and Common-Source Cross-Coupled Pair

Comparative Phase Noise analyses of common-source cross-coupled pair, Colpitts, Hartley and Armstrong differential oscillator circuit topologies, designed in 28 nm bulk CMOS technology in a set of common conditions for operating frequencies in the range from 1 GHz to 100 GHz, are carried out in order to identify their relative performance. The impulse sensitivity function (ISF) is used to carry out qualitative and quantitative analyses of the noise contributions exhibited by each circuit component in each topology, allowing an understanding of their impact on phase noise. The comparative analyses show the existence of five distinct frequency regions in which the four topologies rank unevenly in terms of best phase noise performance. Moreover, the results obtained from the ISF show the impact of flicker noise contribution as the major effect leading to phase noise degradation in nanoscale CMOS LC oscillators.

Comparative analyses of phase noise in 28 nm CMOS LC oscillator circuit topologies: Hartley, Colpitts, and common-source cross-coupled differential pair.

This paper reports comparative analyses of phase noise in Hartley, Colpitts, and common-source cross-coupled differential pair LC oscillator topologies in 28 nm CMOS technology. The impulse sensitivity function is used to carry out both qualitative and quantitative analyses of the phase noise exhibited by each circuit component in each circuit topology with oscillation frequency ranging from 1 to 100 GHz. The comparative analyses show the existence of four distinct frequency regions in which the three oscillator topologies rank unevenly in terms of best phase noise performance, due to the combined effects of device noise and circuit node sensitivity.

Phase Noise comparative analysis of LC oscillators in 28-nm CMOS through the Impulse Sensitivity Function

Comparative Phase Noise (PN) analysis of Hartley, Colpitts and Cross-coupled LC oscillators at 10 GHz in 28-nm CMOS technology is reported. The results of the PN direct plots in the Cadence-SpectreRF design environment are compared with the results obtained by the Impulse Sensitivity Function (ISF). The steps for deriving accurately the ISF are reported and discussed. The results show a very good agreement in a set of conditions, and confirm that the LC cross-coupled differential oscillator exhibits superior PN performance with respect to Colpitts and Hartley, and also that Colpitts exhibits slightly superior performance with respect to Hartley.

67GHz three-spiral transformer CMOS oscillator

This paper presents a 67GHz LC oscillator exploiting a three-spiral transformer and implemented in 65nm bulk complementary metal-oxide-semiconductor technology by STMicroelectronics. The three-spiral transformer allows operating with a lower voltage supply, still obtaining good phase noise performance, and achieving a compact design. Measured performances when supplied with 1.2V are: oscillation frequency of 67GHz, phase noise PN equal to -96dBc/Hz at 1MHz frequency offset from the carrier, power consumption PC equal to 19.2mW and figure of merit FOM equal to -179.7dB/Hz. Measured performances when supplied with 0.6V are: oscillation frequency of 67GHz; PN equal to -88.7dBc/Hz at a 1MHz frequency offset from the carrier; PC equal to 3.6mW and FOM equal to -179.7dB/Hz. Copyright

Phase noise analysis in CMOS differential Armstrong oscillator topology

Summary This paper reports a phase noise analysis in a differential Armstrong oscillator circuit topology in CMOS technology. The analytical expressions of phase noise due to flicker and thermal noise sources are derived and validated by the results obtained through SpectreRF simulations for oscillation frequencies of 1, 10, and 100 GHz. The analysis captures well the phase noise of the oscillator topology and shows the impact of flicker noise contribution as the major effect leading to phase noise degradation in nano-scale CMOS LC oscillators. Copyright

Comparative analyses of phase noise in differential oscillator topologies in 28 nm CMOS technology

This paper reports comparative analyses of phase noise in common-source cross-coupled differential pair, differential Colpitts, Hartley and Armstrong LC oscillator topologies designed in 28 nm CMOS technology for 10 GHz operations. The Impulse Sensitivity Function is used to carry out qualitative and quantitative analyses of the phase noise exhibited by each circuit component in each topology. The analyses show that the lowest phase noise is exhibited by the differential Armstrong topology. Additionally, the results show the impact of flicker noise on phase noise performances.

Transformer-coupled π-network differential CMOS oscillator circuit topology

This paper reports a novel oscillator circuit topology based on a transformer-coupled π-network. As a case study, the proposed oscillator topology has been designed and studied for 60GHz applications in the frame of the emerging fifth generation wireless communications. The analytical expression of the oscillation frequency is derived and validated through circuit simulations. The root-locus analysis shows that oscillations occur only at that resonant frequency of the LC tank. Moreover, a closed-form expression for the quality factor Q of the LC tank is derived which shows the enhancement of the equivalent quality factor of the LC tank due to the transformer-coupling. Last, a phase noise analysis is reported and the analytical expressions of phase noise due to flicker and thermal noise sources are derived and validated by the results obtained through SpectreRF simulations in the Cadence design environment with a 28nm CMOS process design kit commercially available. Copyright

Analyses of phase noise reduction techniques in CMOS Hartley oscillator topology at the mm-waves: Noise filter and optimum current density

This paper reports the analyses of two techniques for phase noise reduction in the CMOS Hartley oscillator circuit topology. Namely, the two techniques, noise filter and optimum current density are investigated with the objective of exploring the potential benefits in the mm-waves frequency range. The design of the circuit topology is carried out in 28 nm bulk CMOS technology by STMicroelectronics. Overall, the analyses show that the adoption of these techniques may lead in principle to a potential phase noise reduction up to 16 dB at a 1 MHz frequency offset for an oscillation frequency of 100 GHz.

Transformer-Based Input Integrated Matching in Cascode Amplifiers: Analytical Proofs

The transformer-based input integrated matching allows the realization of the simultaneous optimum noise and maximum power transfer input impedance matching in cascode amplifiers by exploiting the mutual coupling between the two spirals of an integrated transformer. This technique has been adopted to design LNAs operating in the microwave and millimeter-wave frequency ranges; however, the analytical proofs are still missing. This paper addresses for the first time a complete and in-depth study of the circuit topology and design technique in order to provide the analytical proofs. In-depth analyses are also used to get useful circuit insights, derive effective design equations, and carry out a direct comparison with the most widespread cascode low-noise amplifier with inductive degeneration through circuit design under the same conditions.