Ilias Iliadis

Write amplification analysis in flash-based solid state drives

Write amplification is a critical factor limiting the random write performance and write endurance in storage devices based on NAND-flash memories such as solid-state drives (SSD). The impact of garbage collection on write amplification is influenced by the level of over-provisioning and the choice of reclaiming policy. In this paper, we present a novel probabilistic model of write amplification for log-structured flash-based SSDs. Specifically, we quantify the impact of over-provisioning on write amplification analytically and by simulation assuming workloads of uniformly-distributed random short writes. Moreover, we propose modified versions of the greedy garbage-collection reclaiming policy and compare their performance. Finally, we analytically evaluate the benefits of separating static and dynamic data in reducing write amplification, and how to address endurance with proper wear leveling.

A new intra-disk redundancy scheme for high-reliability RAID storage systems in the presence of unrecoverable errors

Todays data storage systems are increasingly adopting low-cost disk drives that have higher capacity but lower reliability, leading to more frequent rebuilds and to a higher risk of unrecoverable media errors. We propose an efficient intradisk redundancy scheme to enhance the reliability of RAID systems. This scheme introduces an additional level of redundancy inside each disk, on top of the RAID redundancy across multiple disks. The RAID parity provides protection against disk failures, whereas the proposed scheme aims to protect against media-related unrecoverable errors. In particular, we consider an intradisk redundancy architecture that is based on an interleaved parity-check coding scheme, which incurs only negligible I/O performance degradation. A comparison between this coding scheme and schemes based on traditional Reed--Solomon codes and single-parity-check codes is conducted by analytical means. A new model is developed to capture the effect of correlated unrecoverable sector errors. The probability of an unrecoverable failure associated with these schemes is derived for the new correlated model, as well as for the simpler independent error model. We also derive closed-form expressions for the mean time to data loss of RAID-5 and RAID-6 systems in the presence of unrecoverable errors and disk failures. We then combine these results to characterize the reliability of RAID systems that incorporate the intradisk redundancy scheme. Our results show that in the practical case of correlated errors, the interleaved parity-check scheme provides the same reliability as the optimum, albeit more complex, Reed--Solomon coding scheme. Finally, the I/O and throughput performances are evaluated by means of analysis and event-driven simulation.

A flexible shared-buffer switch for ATM at Gb/s rates

Abstract This paper presents the architecture of a very high-speed VLSI packet switch and its performance. The switch, called PRIZMA, is suited for broadband telecommunications, based on ATM, the Asynchronous Transfer Mode. However, the concept is not restricted to ATM-oriented architectural environments. There may be applications within private networks, independent of whether they are ATM-based. There may also be other potential applications such as multiprocessor interconnection. The architecture of the PRIZMA switch follows the architecture of its lower-speed earlier version (H. Ahmadi et al., Int. J. Digital Analog Cabled Syst. 2 (4) (1989) 277–287) to a large degree: It is based on a single-chip switch element that exploits the performance advantage of output queuing and from which larger, self-routing single-stage or multistage switch fabrics can be constructed in a modular way. However, compared to the precursor, higher performance is achieved by output queues that now are configured as a dynamically shared memory. This shared memory can also be expanded by linking multiple switch elements. Owing to novel parallel structures inside the switch element, VLSI implementation is possible for transmission rates on the order of a gigabit per second per port. In the last section of this paper, performance results are presented for a switch in a single-stage configuration as well as for the case of a three-stage switch fabric.

A four-terabit packet switch supporting long round-trip times

This 4-TBPS packet switch uses a combined input- and crosspoint-queued (CICQ) structure with virtual output queuing at the ingress to achieve the scalability of input-buffered switches, the performance of output-buffered switches, and low latency.

Performance of greedy garbage collection in flash-based solid-state drives

In flash-based solid-state drives (SSD) and log-structured file systems, new data is written out-of-place, which over time exhausts the available free space. New free space is created by the garbage-collection process, which reclaims the space occupied by invalidated data. The write amplification, incurred because of the additional write operations performed by the garbage-collection mechanism is a critical factor that negatively affects the lifetime and endurance of SSDs. We develop two complementary theoretical models of the SSD operation for uniformly-distributed random small user writes: a Markov chain model, which is useful to explore the performance characteristics of small and medium-sized systems, and a second model that captures the behavior of large systems. The combination of both models allows us to comprehensively characterize the system operation and behavior. Results of theoretical and practical importance are analytically derived and confirmed by means of simulation. Our results demonstrate that (i) as the system occupancy increases, the write amplification increases; (ii) as the number of blocks increases, the write amplification decreases and approaches a lower bound; and (iii) as the number of pages contained in a block increases, the write amplification increases and approaches an upper bound. They also show that, for large systems, the number of free pages reclaimed by the greedy garbage-collection mechanism after each block recycling takes one of two successive values, which provides a quasi-deterministic performance guarantee.

Disk scrubbing versus intra-disk redundancy for high-reliability raid storage systems

Two schemes proposed to cope with unrecoverable or latent media errors and enhance the reliability of RAID systems are examined. The first scheme is the established, widely used disk scrubbing scheme, which operates by periodically accessing disk drives to detect media-related unrecoverable errors. These errors are subsequently corrected by rebuilding the sectors affected. The second scheme is the recently proposed intradisk redundancy scheme which uses a further level of redundancy inside each disk, in addition to the RAID redundancy across multiple disks. Analytic results are obtained assuming Poisson arrivals of random I/O requests. Our results demonstrate that the reliability improvement due to disk scrubbing depends on the scrubbing frequency and the workload of the system, and may not reach the reliability level achieved by a simple IPC-based intra-disk redundancy scheme, which is insensitive to the workload. In fact, the IPC-based intra-disk redundancy scheme achieves essentially the same reliability as that of a system operating without unrecoverable sector errors. For heavy workloads, the reliability achieved by the scrubbing scheme can be orders of magnitude less than that of the intra-disk redundancy scheme.

Designing a Crossbar Scheduler for HPC Applications

A crucial part of any high-performance computing (HPC) system is its interconnection network. Corning and IBM are jointly developing a demonstration interconnect based on optical cell switching with electronic control. The Corning-IBM joint optical shared memory supercomputer interconnect system (Osmosis) project explores the opportunity to advance the role of optical-switching technologies in such systems. Key innovations in the scheduler architecture directly address the main HPC requirements: low latency, high throughput, efficient multicast support, and high reliability

Analysis of packet switches with input and output queuing

A single-stage nonblocking N*N packet switch with both output and input queuing is considered. The limited queuing at the output ports resolves output port contention partially. Overflow at the output queues is prevented by a backpressure mechanism and additional queuing at the input ports. The impact of the backpressure effect on the switch performance for arbitrary output buffer sizes and for N to infinity is studied. Two different switch models are considered: an asynchronous model with Poisson arrivals and a synchronous model with Bernoulli arrivals. The investigation is based on the average delay and the maximum throughput of the switch. Closed-form expressions for these performance measures are derived for operation with fixed size packets. The results demonstrate that a modest amount of output queuing, in conjunction with appropriate switch speedup, provides significant delay and throughput improvements over pure input queuing. The maximum throughput is the same for the synchronous and the asynchronous switch model, although the delay is different. >

Low-latency pipelined crossbar arbitration

Heuristic, parallel, iterative matching algorithms for input-queued cell switches with virtual output queuing require O(log N) iterations to achieve good performance. If the hardware implementation of the number of iterations required is not feasible within the cell duration, the matching process can be pipelined to obtain a matching in every cell time slot. However, existing approaches incur a substantial latency penalty due to the way the pipelining is performed, which renders them unattractive in latency-sensitive applications such as parallel computer interconnects. We introduce a new class of pipelined matching algorithms that can be based on any existing iterative matching algorithm, makes the minimum latency independent of the pipeline depth, and is highly amenable to distributed implementation. Our simulation results confirm that specific instances of this class achieve significantly lower average latency throughout the load range than existing schemes do. We also propose an instantiation of the scheme that, in addition, significantly improves the performance with nonuniform traffic.

Optimal PNNI complex node representations for restrictive costs and minimal path computation time

The private network-to-network interface (PNNI) protocol, which specifies how topology information is to be distributed in an ATM network, allows ATM switches to be aggregated into clusters called peer groups. Outside of a peer group its topology is aggregated into a single logical node. This method can be applied recursively so that PNNI can hierarchically aggregate network topology state information. To provide good accuracy in choosing optimal paths in a PNNI network, the PNNI standard provides a way to represent a peer group with a structure called the complex node representation. It allows the cost of traversing the peer group between any ingress and egress to be advertised in a compact form. Complex node representations using a small number of links result in a correspondingly short path computation time and therefore in good performance. It is, therefore, desirable that the complex node representation contains as few links as possible. This paper considers the class of complex node representations for which the path computation time is minimal. It assumes that the path selection is based on restrictive costs, such as bandwidth, and considers the symmetric case. It presents a method for constructing the set of the optimal complex node representations in the sense that they use the minimum possible number of links. Central to the development of this method is the establishment of the optimal substructure property of the optimal complex node representations.