Ilija Hadzic

Adaptive packet selection for clock recovery

Packet delay variation (PDV) is a dominant source of noise in packet-based synchronization systems. To filter this type of noise, many clock recovery algorithms select packets based on the sample-minimum statistic of the network transit time. Although such a filter can be very effective in certain types of networks, there are just as many networks and background traffic patterns for which sample-minimum is far from optimal. In this paper, we propose a filter that dynamically evaluates multiple packet selection criteria and selects the one that currently minimizes the noise. We also present the results of an experimental evaluation of the new adaptive filter.

On packet selection criteria for clock recovery

Many packet-based clock recovery algorithms use only a subset of timing packet arrivals to discipline the local oscillator. One commonly used selection process is to partition the time into non-overlapping windows and, for each window, select only the one that had the smallest network transit time. This process is a non-linear filter, developed mostly based on intuition and widely accepted by many researchers and developers without much formal analysis. In this paper, we analyze the output statistics of such a filter, provide a closed-form expression for some commonly observed packet delay profiles, and back the results with experimental data. We also point out some network scenarios where usage of the filter is not well justified.

Improving IEEE 1588v2 clock performance through controlled packet departures

Packet delay variation (PDV) is the dominant impairment in packet-based synchronization systems. One way to mitigate its effect is to apply advanced filtering techniques on phase error information derived from packet arrival events. In this letter we consider an alternative approach in which the backpressure to the background traffic source is coordinated with timing packet generation such that the PDV is completely eliminated. Although the proposed method is limited to tree network topologies, the results are notable due to complete elimination of the PDV noise even if the background traffic load approaches 100%.

Hierarchical MAC address space in public Ethernet networks

Service providers are showing strong interest in building all-Ethernet public metropolitan networks that would compete with (and eventually replace) the existing network infrastructures based on SONET, Frame Relay, ATM and similar technologies. The main driving factor is the cost, as Ethernet-based technology is typically cheaper than any others available on the market. Despite successful initial laboratory and field deployment tests, there are still many unresolved issues related to metropolitan-scale Ethernet, such as the appropriateness of a spanning tree algorithm, broadcast flooding and MAC address table explosion in core switches. This paper focuses on the problem of MAC address table explosion by introducing a hierarchy into the address space, through Ethernet-inside-Ethernet packet encapsulation. The encapsulation allows core switches to be standard Ethernet switches, while the edge switches implement concepts presented in this paper. The proposed concept is thus transparent to the existing infrastructure and thereby allows building the network using readily available low-cost layer-2 switches.

Synthesis of high-performance packet processing pipelines

Packet editing is a fundamental building block of data communication systems such as switches and routers. Circuits that implement this function are critical and define the features of the system. We propose a high-level synthesis technique for a new model for representing packet editing functions. Experiments show our circuits achieve a throughput of up to 40Gb/s on a commercially available FPGA device, equal to state-of-the-art implementations

3D rendering in the cloud

Many modern applications and window systems perform three-dimensional (3D) rendering. For a cloud system to support such applications, that 3D rendering must be performed in the cloud, because the end-user equipment cannot be relied upon to contain the necessary rendering hardware. All systems that perform 3D rendering in the cloud are faced with two fundamental and related problems: 1) How to enable an arbitrary number of users to produce rendered pixel streams, and 2) how to transfer those pixel streams out of the servers frame buffers and into one or more encoders, for transmission to the user. We have implemented a new form of display virtualization that solves both of these problems in a low-level and transparent manner. Using our display virtualization (which we call the virtual cathode ray tube controller (VCRTC)), the cloud system can support an arbitrary number of pixel streams (bounded only by memory and bandwidth resources), and it can dynamically associate those streams with encoders. VCRTCs are completely transparent to the applications: No application needs to be modified, recompiled, or even relinked to use VCRTCs. Because they are low-level and transparent, VCRTCs are also a general mechanism with utility beyond cloud systems.

Synthesis and Optimization of Pipelined Packet Processors

We consider pipelined architectures of packet processors consisting of a sequence of simple packet-processing modules interconnected by first-in first-out buffers. We propose a new model for describing their function, an automated synthesis technique that generates efficient hardware for them, and an algorithm for computing minimum buffer sizes that allow such pipelines to achieve their maximum throughput. Our functional model provides a level of abstraction familiar to a network protocol designer; in particular, it does not require knowledge of register-transfer-level hardware design. Our synthesis tool implements the specified function in a sequential circuit that processes packet data a word at a time. Finally, our analysis technique computes the maximum throughput possible from the modules and then determines the smallest buffers that can achieve it. Experimental results conducted on industrial-strength examples suggest that our techniques are practical. Our synthesis algorithm can generate circuits that achieve 40 Gb/s on field-programmable gate arrays, equal to state-of-the-art manual implementations, and our buffer-sizing algorithm has a practically short runtime. Together, our techniques make it easier to quickly develop and deploy high-speed network switches.

Nonuniform Linear Regression With Block-Wise Sample-Minimum Preprocessing

We analyze the statistical properties of slope estimates obtained from linear regression with sample-minimum Erlang variates. The sample-minimum of sequential blocks has the effect of introducing nonuniform time samples. We show that this nonuniformity has negligible effect on the slope estimate variance, but introduces a spurious low-frequency component in the power spectrum, which can be detrimental for low-bandwidth tracking applications. The analysis shows that this effect can be moderated by choosing a sufficiently large number of sample-minimum output samples in the linear regression. These results are useful, for example, in clock synchronization over packet networks, where the random variates model packet arrival times.

Low-Level Frame-Buffer Scraping for GPUs in the Cloud

We describe and evaluate a software-only implementation of a novel mechanism for accessing and streaming GPU-rendered content from the cloud to low-end user devices. The unique properties of our implementation enable the trivial cloud-deployment of graphics-intensive applications, even ones that were not originally intended to run in the cloud. We achieve this goal by creating virtual GPU nodes that appear to the application like hardware devices, but that do not incur the overhead of virtualization. The low-level access to the frame buffer maximizes the number of applications that work out-of-the-box without the system imposing any specific display manager or windowing system.

A simple analysis of linear regression with sample-minimum Erlang variates

We analyze the statistical properties of slope estimates obtained from linear regression with sample-minimum Erlang variates. The sample-minimum of sequential blocks has the effect of introducing non-uniform time samples. It is shown that this non-uniformity has negligible effect on the slope estimate variance, but introduces a spurious low-frequency component in the power spectrum, which may be detrimental for ultra-low-bandwidth tracking applications. The analysis shows that this effect can be moderated by choosing a sufficiently large number of sample-minimum output samples in the linear regression. These results are useful, for example, in clock synchronization over packet networks, where the random variates model packet arrival times.