In-Shek Hsu

A comparison of VLSI architecture of finite field multipliers using dual, normal, or standard bases

Three different finite-field multipliers are presented: (1) a dual-basis multiplier due to E.R. Berlekamp (1982); the Massey-Omura normal basis multiplier; and (3) the Scott-Tavares-Peppard standard basis multiplier. These algorithms are chosen because each has its own distinct features that apply most suitably in particular areas. They are implemented on silicon chips with NMOS technology so that the multiplier most desirable for VLSI implementation can readily be ascertained. >

The VLSI design of a single chip for the multiplication of integers modulo a Fermat number

Multiplication is central in the implementation of Fermat number transforms (FNT) and other residue number algorithms. There is need for a good multiplication algorithm which can be realized easily on a VLSI chip. In this paper, the Leibowitz multiplier [1] is modified to realize multiplication in the ring of integers modulo a Fermat number. The advantage of this new algorithm over Leibowitzs algorithm is that Leibowitzs algorithm takes modulo after the product of multiplication is obtained. Hence time is wasted. In this new algorithm, modulo is taken in every bit operation when performing multiplication. Therefore no time is wasted in this respect. Furthermore, this algorithm requires only a sequence of cyclic shifts and additions. The design for this new multiplier is regular, simple, expandable, and therefore, suitable for VLSI implementation.

A pipeline design of a fast prime factor DFT on a finite field

A conventional prime factor discrete Fourier transform (DFT) algorithm of the Winograd type is used to realize a discrete Fourier-like transform on the finite field GF(q/sup /n). A pipeline structure is used to implement this prime-factor DFT over GF(q/sup /n). This algorithm is developed to compute cyclic convolutions of complex numbers and to aid in decoding the Reed-Solomon codes. Such a pipeline fast prime-factor DFT algorithm over GF(q/sup /n) is regular, simple, expandable, and naturally suitable for most implementation technologies. An example illustrating the pipeline aspect of a 30-point transform over GF(q/sup /n) is presented. >

An FPT algorithm with a modularized structure for computing 2-D cyclic convolutions

The fast polynomial transform (FPT) for computing 2-D cyclic convolutions is modularized into identical modules. In the new method, the 1-D cyclic polynomial convolution is decomposed into cycle convolutions of polynomials, all of the same length. Thus, only FPTs and FFTs of the same length are required. As a consequence, the architecture is more regular and naturally suitable for a VLSI implementation. >

A single chip VLSI Reed-Solomon decoder

A new VLSI design of a pipeline Reed-Solomon decoder is presented. The transform decoding technique used in a previous design is replaced by a simple time domain algorithm. A new architecture which realizes such algorithm permits efficient pipeline processing with a minimum of circuits. A systolic array is also developed to perform erasure corrections in the new design. A modified form of Euclids algorithm is developed with a new architecture which maintains a real-time throughput rate with less transistors. Such improvements results in both an enhanced capability and significant reduction in silicon area, thereby making it possible to build a pipeline (255,223) RS decoder on a single VLSI chip.

A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with fermat numbers

A quadratic-polynominal Fermat residue number system (QFNS) was used to compute complex integer multiplications in [1]. The advantage of such a QFNS is that a complex integer multiplication requires only two integer multiplications. In this correspondence, a new type of Fermat number multiplier is developed which eliminates the initialization condition of the previous method. It is shown that the new complex multiplier can be implemented on a single VLSI chip. Such a chip is designed and fabricated in CMOS-pw technology.

The VLSI Design of an Error-Trellis Syndrome Decoder for Certain Convolutional Codes

In this paper a recursive algorithm using the error-trellis decoding technique is developed to decode certain convolutional codes (CCs). An example, illustrating the VLSI architecture of such a decoder, is given for a dual-k CC. It is demonstrated that such a decoder can be realized readily on a single chip with NMOS technology.

VLSI residue multiplier modulo a Fermat number

Multiplication is central in the implementation of Fermat number transforms (FNT) and other residue number algorithms. There is need for a good multiplication algorithm which can be realized easily on a VLSI chip. In this paper, the Leibowitz multiplier [1] is modified to realize multiplication in the ring of integers modulo a Fermat number. The advantage of this new algorithm over Leibowitzs algorithm is that Leibowitzs algorithm takes modulo after the product of multiplication is obtained. Hence time is wasted. In this new algorithm, modulo is taken in every bit operation when performing multiplication. Therefore no time is wasted in this respect. Furthermore, this algorithm requires only a sequence of cyclic shifts and additions. The design for this new multiplier are regular, simple, expandable and therefore, suitable for VLSI implementation.

The VLSI design of a single chip for the multiplication of integers modulo a fermat number

Multiplication is central in the implementation of Fermat Number Transforms (FNT) and other residue number algorithms. There is need for a good multiplication algorithm which can be realized easily on a VLSI chip. In this paper, the Leibowitz multiplier [1] is modified to realize multiplication in the ring of integers modulo a Fermat number. The advantage of this new algorithm over Leibowitzs algorithm is that Leibowitzs algorithm takes modulo after the product of multiplication is obtained. Hence time is wasted. In this new algorithm, modulo is taken in every bit operation when performing multiplication. Therefore no time is wasted in this respect. Furthermore, this algorithm requires only a sequence of cyclic shifts and additions. The design for this new multiplier are regular, simple, expandable and therefore, suitable for VLSI implementation.

A VLSI architecture for performing finite field arithmetic with reduced table lookup

Abstract A new table lookup method for finding the log and antilog of finite field elements has been developed by Glover. The method makes use of several smaller tables, and is based on the Chinese remainder theorem. It often results in a significant reduction in the memory requirements of the problem. A VLSI architecture is developed here for a special case of this new algorithm to perform finite field arithmetic including multiplication, division, and the finding of an inverse element in the finite field.