In-Wook Cho

Novel Select Gate Lateral Coupling Single Poly eNVM for an HVCMOS Process

We present a novel select gate (SG) lateral coupling embedded nonvolatile memory without any additional steps on a 90-nm high-voltage CMOS process. Usually, the SG coupling devices use a complex double poly process. However, continuing technology shrinkage makes the lateral coupling method possible for a single poly process. The SG of the novel cell is designed to function as a control gate and an SG at the same time, using only lateral capacitance coupling. Because of this distinct cell structure and operating principle, the memory cell has relatively small cell size, over-erase free, and multitime programmable features. The proposed cell is programmed by channel hot electron method and erased by band-to-band tunneling-assisted hot hole method, resulting in a 20- μs programming time and 100-ms erasing time. In addition, using this condition, we can achieve over 3 V threshold voltage (VT) window over 500 cycles and an estimated over 10 year retention lifetime at 85 °.

HB1340 ℄ Advanced 0.13um BCDMOS technology of complimentary LDMOS including fully isolated transistors

In this work, we developed a HB1340-0.13um BCD technology of the complimentary LDMOS including fully isolated structure device with dual drift layer. We could achieve LDMOS with best-in-class trade-off between specific on-resistance and breakdown voltage by its optimized drain engineering. The HB1340 process in 0.13um 1.5V/5V/6V CMOS technology platform can provide various kinds of high voltage devices such as LDMOS, DEMOS from 12V to 40V and fully isolated 24V LDNMOS for mobile and display power application. High gain BJT, Zener diode, high voltage diode, high resistor, MIM and EEPROM are also have been integrated in smart power technology.

A proposal of LDMOS using Deep Trench poly field plate

In this paper, we developed Deep Trench structure of LDMOS instead of STI in conventional one, with 0.18um 60V BCD process. By forming vertical drift region using Deep Trench, we achieved lower Ron.sp from cell pitch shrink while BVdss does not change. As a result we achieved 76V BVdss and 49.3 mohm*mm2 Ron.sp of low side 60V rated LDNMOS.

Operating principle verification and scaling benefits of SGLC eNVM

The authors demonstrated and verified the operation of a SGLC eNVM cell using 3D and 2D TCAD simulations. In addition, we have explained the benefits of the SGLC NVM cell as CMOS process design rules shrink. The novel SGLC cell shows a smaller size than 6T SRAM for beyond the 65 nm technology node. The SGLC cell shows ideal characteristics for eNVM, such as a fast program speed, multi-time programmable support, over-erase free features as well as an SRAM comparable cell size without any additional process steps.

Single-Poly Embedded NVM Solution for Analog Trimming and Code Storage Applications

We report a single-poly embedded nonvolatile memory (eNVM) solution for analog trimming and code storage applications using a 0.13-μm BCDMOS process. Each cell has its own merits and demerits, depending on structure and operation methods. For analog trimming purposes, a conventional n-well coupling Fowler-Nordheim tunneling cell with a large unit cell size of 88 μm2 is used. On the other hand, a select gate lateral coupling (SGLC) cell for code storage purposes has a much smaller unit cell size of 2.82 μm2, which is comparable to the size of SRAM. The SGLC cell is fabricated using a combination of only 1.5-V and 5-V transistor-related processes for channel hot electron injection programming. The SGLC cell exhibits a high programming speed of 100 μs and is over-erase-free, which is suitable for a NOR array structure. In addition, both cells also had a retention lifetime of more than 10 years. Thus, these cells can be fabricated to match the requirements of various eNVM applications.

Control Plug Lateral Coupling Memory Cell Utilizing Uniform Channel Fowler–Nordheim Operation

In this letter, we propose a control-plug (CP) structure logic nonvolatile memory (LNVM) fabricated by a standard logic CMOS process for mobile applications with low-power-consumption requirement. The operating concept of this cell is based on the use of a lateral capacitance coupling between a bar-type CP and a floating gate. Owing to the unique bar-type CP-coupling method and CP-sharing cell array structure, the novel cell has a coupling ratio of over 94% with the lowest fill factor of 344 as a Fowler-Nordheim (FN)-operated LNVM. Furthermore, because of the high coupling ratio and divided-bias operating method, this cell utilizes a uniform-channel FN tunneling program and erase method using a 3.3 V logic peripheral overdrive tolerable voltage of 5.5 V.

Characteristics comparison of standard logic and HVCMOS processed SGLC embedded NVM

The novel select gate lateral coupling (SGLC) cell has a single poly structure and operates using a lateral coupling between the floating gate (FG) and the select gate (SG) without additional processes on a base platform. In this paper, we have fabricated a pure logic CMOS processed SGLC cell for the first time and compared it with an HVCMOS processed SGLC cell. Because of the thinner gate oxide, the pure logic process fabricated SGLC cell has a lower coupling value than that of the HVCMOS process fabricated cell. However, the logic CMOS process fabricated cell shows a higher current performance than the HVCMOS process fabricated cell having a thicker gate oxide. Thanks to the inverse relationship between the coupling ratio and cell current, and the additional back bias effect, the logic CMOS processed cell gives comparable performance in terms of the programming speed, program-erase threshold voltage (VT) window and cell current. Both types of cells show more than 10 years of data retention lifetime at 85°C.

Proposal of 130nm-60V rated fully isolated LDNMOS with double Epi process

In this paper, we developed 60V rated fully isolated LDNMOS which can be available under negative bias condition. Double epi process for obtaining higher BVdss, PBL (p+ buried layer) for retarding punch through and NBL-2 (n+ buried layer) for a role of electrically connecting NBL-1 are adopted to achieve 60V rated fully isolated LDNMOS. This optimized device has characteristics of Ron.sp 55mohm*mm2 and BVdss 66V. We could also develop 90V rated high side LDMOS with Ron.sp 210mohm*mm2 and BVdss 110V through this same double epi process.

A Study of Vertical Thin Poly-Si Channel Transfer Gate Structured CMOS Image Sensors

In this letter, the image characteristics of CMOS image sensor (CIS) pixels using a vertical thin poly-Si channel (VTPC) transfer gate (TG) are established for the first time. The study of three-dimensional (3D) structures in the image sensor field has been started by 3D Flash memories. By adopting the poly-Si channel fabrication concept of 3D NAND flash memories—appropriately modified to fit the requirements of a TG in CIS pixel applications—the VTPC structure effectively suppresses the grain boundary effect. The VTPC-TG performance improves as the poly-Si channel becomes thinner. The possibility of implementing 3D pixel-based CIS is confirmed by applying the fabricated VTPC-TG to a mass-produced 1.12-

Epitaxial growth and diffusion characteristics analysis of vertical thin poly-Si channel transfer gate structured pixels for 3D CMOS image sensor

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