Inad A. Aljarrah

Image Mosaicing Using Binary Edge Detection Algorithm in a Cloud-Computing Environment

Image Mosaicing is an image processing technique that arises from the need of having a more realistic view of the real world wider than the view captured by the lenses of the available cameras. In this paper, a sequence of images will be mosaiced using binary edge detection algorithm in a cloud-computing environment to improve processing speed and accuracy. The authors have used Platform as a Service PaaS to provide a number of nodes in the cloud to run the computational intensive image processing and stitching algorithms. This increased the processing speed as most of image processing algorithms deal with every single pixel in the image. Message Passing Interface MPI is used for message passing among the compute-nodes in the cloud and a MapReduce technique is used for image distribution and collection, where the root node is used as reducer and the others as mappers. After applying the algorithm on different sequence of images and different machines on JUST cloud, the authors have achieved high mosaicing accuracy, and the execution time has been improved when comparing it with sequential execution on the images.

Implementing image processing algorithms in FPGA hardware

This paper describes an efficient FPGA based hardware design for different image processing, enhancement, and filtering algorithms. FPGAs are often used as implementation platforms for real-time image processing applications because their structure is able to exploit spatial and temporal parallelism. The approach used is a windowing operator technique to traverse the pixels of an image, and apply the filters to them. As image sizes bit depth grow larger, software becomes less useful and real-time hardware systems are needed to take their place. The results are obtained for image size of 585×450, but the approach discussed can be used for images of any size, as long as the FPGA memory will hold it. The implementation was created with the Xilinx Spartan-6 FPGA on a Nexys3 board in mind.

Automated system for Arabic optical character recognition

In this paper an Arabic Optical Character Recognition system is implemented. The system takes a scanned image of an Arabic text as an input and generates an editable text out of it. The system starts by segmenting the document which is presented as an image into lines, then each line is also segmented into separate words, after that each word is further segmented to sub-words. Each word or sub-word is segmented into separate characters, and then a features extraction process is applied on each character to calculate its features vector. The feature vector is then compared with templates of feature vectors for each of the Arabic alphabet with their variations. The minimum distance classifier is used in the classification stage. Promising results are achieved regardless that Arabic Optical Character Recognition is considered many times harder to handle than its counterparts in other languages like English due to the continuity between the letters in the same word.

An Automated Multiple Choice Grader for Paper-Based Exams

In this paper an automated multiple choice grader for paper-based exams is implemented. The system consists of two main parts, a software program and a document feeder scanner. The exam papers are fed to the scanner which scans them one by one and send them as an input to the software. The software program recognizes the student Identification Number (ID) and the answers for each exam paper and reports the final results in an Excel sheet. The system starts by applying an aligning procedure and segmenting the scanned image in order to extract form number, student ID, and answers boxes, then a pre-processing step that handles all irregular cases of input is implemented; where in this step a best possible shape that results in the highest recognition accuracy is gained. After getting a proper separated characters and numbers, a feature extraction process is applied on each character/number to calculate its feature vector. The feature vector is then compared with templates of feature vectors for each of the answers choices and numbers with their variations, where both characters and numbers are in English language. After recognizing all the answers and all ID number digits; the system starts grading the student paper and comparing student answer with the pre-entered key answers. A recognition rate of 95.58 % is attained.

An automatic intelligent system for diagnosis and confirmation of Johne's disease

Johnes disease is one of the most widespread bacterial diseases of domestic animals. It causes yearly losses of billions of dollars worldwide. In this paper an automatic intelligent computer-aided system is proposed for the diagnosis of Johnes disease, the system uses image analysis and computer vision techniques to extract features from two different microscopic images, then those features are classified using neural networks and K-nearest neighbour K-NN techniques to diagnose Johnes disease. The proposed system employs histopathological examination to extract 192 different texture features. The features are then reduced into only 8 features and classified using artificial neural networks ANN. The acid fast stain test is used to confirm the positive cases. The construction and testing of both models are carried out using a total of 294 microscopic images, 194 images for the histopathological examination test which produces an overall accuracy of 98.33%. The other 100 images are used for the acid fast stain test, and it achieves an accuracy of 96.97%.

Efficient Low-Power Compact Hardware Units for Real-Time Image Processing

This paper presents efficient low-power compact hardware designs for common image processing functions including the median filter, smoothing filter, motion blurring, emboss filter, sharpening, Sobel, Roberts, and Canny edge detection. The designs were described in Verilog HDL. Xilinx ISE design suite was used for code simulation, synthesis, implementation, and chip programming. The designs were all evaluated in terms of speed, area number of LUTs and registers, and power consumption. Post placement and routing Post-PAR results show that they need very small area and consume very little power while achieving good frame per second rate even for HDTV high resolution frames. This makes them suitable for real-time applications with stringent area and power budgets.