Inmaculada Pardines

Shop&Go: TSP heuristics for an optimal shopping with smartphones

Mobile technology has been under constant growth in last years. The emergence of smartphones has encouraged the development of a wide variety of mobile applications. Some of them are related to daily tasks. In this regard, we propose the Shop&Go mobile application which allows a supermarket customer to do the shopping covering the shortest distance. An analysis of the routing problem applied to an efficient way of doing the shopping is made. A map with items distribution and distances between products is provided by the supermarket. Based on these information two heuristics have been proposed to do the shopping following the optimum path. Both heuristics have been compared, proving that neither of them can be defined as the best one in all cases. The products in the shopping list determine which is the best solution for each case. Therefore, both algorithms have been included in our application, letting the user decide which route he/she wants to follow. Shop&Go has also other functionalities which are extensively described in the paper. Simulations over an HTC Desire mobile are shown to demonstrate the proper tool operation. Finally, a study of consumer acceptance has been made to know its possibilities of success in the mobile technology market.

Minimizing the load redistribution cost in cluster architectures

In this work, we deal with the problem of minimizing the load redistribution cost in parallel implementations for cluster architectures. Due to the importance of the network latency in this kind of systems, the redistribution cost is primarily depending on the maximum number of messages sent or received by a processor. The load redistribution is a NP-hard problem similar to the multiple knapsack problems. Three heuristics are proposed to solve the problem in a global context, and a comparison is made to emphasize their characteristics. In a parallel application, it is important to decide whether it is efficient or not to carry out the workload redistribution. This decision is taken comparing the cost of the load imbalance and the communication overheads associated with the load balancing heuristic. Depending on these costs, a theoretic value of imbalance from which the redistribution is profitable is defined. Experimental results show the accuracy of our proposals.

DSPONE48: A methodology for automatically synthesize HDL focus on the reuse of DSP slices

Abstract This work proposes a methodology to synthesize arithmetic operations maximizing the reuse of the DSP48E1 blocks presented in the new reconfigurable architectures. The input for DSPONE48 is a VHDL code without any reference to the FPGA hardware resources. This input code is modified, so the synthesis tool is able to implement it with DSP slices. In order to achieve this objective we use DSP block instantiation templates and we encourage the use of SIMD mode within the DSP block. This methodology replaces automatically the most common arithmetic operations by their equivalents on DSP slices. The methodology guarantees that the new code preserves the functionality and the number of execution cycles of the original design. Experimental results, on a Virtex 7 FPGA, show that the designs obtained by DSPONE48 use less DSPs than those obtained automatically by Xilinx ISE or Vivado. Moreover, these designs have lower area and higher frequency.

Collaborative Recommendation System for Environmental Activities Management Mobile Application

The use of a collaborative recommendation system applying fuzzy linguistic techniques is proposed in this paper. This system is included in a mobile application that manages information and the enrollment process in the activities of the Environmental Educational Program of the City of Madrid. This tool informs the user of all activities: workshops, routes, exhibitions, gardening, etc., that are made in the Environmental Education Centres of the City of Madrid. Because of the extra information that the user can receive is essential to have a system to provide the activities that may be most interesting for the user. These activities are selected based on the user’s preferences profile and the register with the ratings of the activities previously performed by other users, especially, the evaluations of those with a similar profile.

Shop&Go: The Routing Problem Applied to the Shopping List on Smartphones

Mobile applications have achieved a great development in the past years. Some of the existing tools are useful for carrying out daily tasks. In this regard, we propose in this paper a mobile application, called Shop&Go, to do the shopping in a supermarket covering the shortest distance. This kind of problems is a classic paradigm from the field of operational research. We propose two heuristics to obtain the optimum path to do the shopping. The distances and the products layout are obtained from a map previously provided by the supermarket. We have compared both heuristics, proving that any of them can achieve the best solution depending on which products are in the shopping list. Therefore, we have decided to include both algorithms in our tool, leaving to the user the decision of which of the solution paths to take. The application has also other functional requirements which are described in the paper. Simulations of how the tool is working over an HTC Desire mobile are shown.

Efficient Dynamic Load Balancing Strategies for Parallel Active Set Optimization Methods

In this paper three strategies are described to restore dynamically the load balancing in parallel active set optimization algorithms. The efficiency of our proposals is shown by comparison with other heuristics described in related works, such as the classical Bestfit and Worstfit methods. The computational cost due to the load unbalancing in the parallel code and the communication overheads associated with the most efficient load balancing strategy are analyzed and compared in order to establish whether the distribution is convenient or not. Experimental results on a distributed memory system, the Fujitsu AP3000, highlight the accuracy of our estimations.

Radiation-hardened DSP configurations for implementing arithmetic functions on FPGA

This paper presents a study of different implementations of arithmetic operations on FPGAs. Radiation vulnerability has been analyzed for each implementation using the fault injection platform NESSY. Results in terms of area, delay and reliability are presented. We propose to build a library of HDL templates taking into account the performed tests. This library is used during the design process with a synthesis tool that implements digital circuits as reliable as possible. Experimental results show that implementations using DSP slices are the ones which achieve better results.

Online Evaluation Methodology of Laboratory Sessions in Computer Science Degrees

This paper presents a proposal for assessing the laboratory sessions of a subject of the first year in computer science degrees. This methodology is based on online short-answer exam questions related to the concepts studied in each session. After analyzing the academic results of a large group of students, we may conclude that this way of evaluating knowledge is precise. The obtained grades neither underestimate nor overestimate the students work, being similar to the ones achieved in a final exam. Moreover, there is continuous feedback, which allows the teacher to go into detail about those aspects of the subject that students have not understood.

A RECONFIGURABLE MODULAR ARCHITECTURE TO EXPLOIT WORD-LEVEL PARALLELISM

Contemporary memory system design aims to achieve high performance and low energy consumption at a reasonable cost. To balance these requirements, we propose a modular reconfigurable architecture to design memories over FPGAs. The proposed memory system can be reconfigured taking into account: the number of words, the word size of the data, the number of physical memory banks and the number of ports of the banks. Different operating modes have been defined, each one implying a certain configuration for the memory system. Simulations of these modes show the performance of our reconfigurable memory in terms of timing and power consumption.