Ioannis Sarkas

A Fundamental Frequency 120-GHz SiGe BiCMOS Distance Sensor With Integrated Antenna

This paper describes the first fundamental frequency single-chip transceiver operating at -band. The low-IF monostatic transceiver integrates on a single chip two 120-GHz voltage-controlled oscillators (VCOs), a 120-GHz divide-by-64 chain, two in-phase/quadrature (IQ) receivers with phase-calibration circuitry, a variable gain transmit amplifier, an antenna directional coupler, a patch antenna, bias circuitry, a transmit power detector, and a temperature sensor. A quartz antenna resonator with 6-dBi gain and simulated 50% efficiency is placed directly above the on-chip patch to transmit and receive the 120-GHz signals. The circuit with the above-integrated-circuit antenna occupies an area of 2.2 mm 2.6 mm, consumes 900 mW from 1.2- and 1.8-V supplies, and was wire-bonded in an open-lid 7 mm 7 mm quad-flat no-leads package. Some transceiver performance parameters were characterized on the packaged chip, mounted on an evaluation board, while others, such as receiver noise figure and VCO phase noise at the 120-GHz output were measured on circuit breakouts. The AMOS-varactor VCOs have a typical phase noise of at 1-MHz offset and a tuning range of 115.2-123.9 GHz. The receiver gain and the transmitter output power are each adjustable over a range of 15 dB with a maximum transmitter output power of 3.6 dBm. The receiver IQ phase difference, measured at the IF outputs of the packaged transceiver, is adjustable from 70° to 110°, while the amplitude imbalance remains less than 1 dB. The receiver breakout gain and double-sideband noise figure are 10.5-13 and 10.5-11.5 dB, respectively, with an input compression point of . Several experiments were conducted through the air over distances of up to 2.1 m with a focusing lens placed above the packaged chip.

An 18-Gb/s, Direct QPSK Modulation SiGe BiCMOS Transceiver for Last Mile Links in the 70–80 GHz Band

This paper describes a single-chip, 70-80 GHz wireless transceiver utilizing a direct mm-wave QPSK modulator. The transceiver was fabricated in a 130 nm SiGe BiCMOS technology and can operate at data rates in excess of 18 Gb/s. The peak gain of the zero-IF receiver is 50 dB, the double sideband noise figure remains below 7 dB, while the 3-dB receive-chain bandwidth extends from DC to over 6 GHz. The differential transmitter achieves a maximum output power of +9 dBm. The total power consumption of the 1.9 mm × 1.1 mm transceiver is 1.2 W from 1.5, 2.5 and 3.3 V power supplies, including the 4 × 20-Gb/s PRBS generator.

A 2-Bit, 24 dBm, Millimeter-Wave SOI CMOS Power-DAC Cell for Watt-Level High-Efficiency, Fully Digital m-ary QAM Transmitters

A high-efficiency, large output-power, mm-wave digital transmitter architecture is proposed for high data rate m-ary QAM transmission. Because it operates entirely in digital mode, without any matching networks, it is scalable in frequency up to at least 50 GHz and portable to future generations of CMOS technologies. It consists of n broadband mm-wave IQ power-DAC pairs directly modulated in amplitude and phase by 4 x n independent digital data streams. The output signals combine in free space to form a programmable ASK, BPSK, QPSK, and m-ary QAM mm-wave transmitter. Several proof-of-concept circuits with one DAC cell, and with one and two IQ pairs of DAC cells were fabricated in 45-nm SOI CMOS. Using a series-stacked differential output stage with four cascoded n-MOSFETs driven in saturation by a CMOS-inverter chain, each power-DAC cell demonstrates a 24.3 dBm output power with 21.3% drain efficiency and 14.6% PAE, at 45 GHz directly into 50-Ω loads. The peak drain efficiency is 30% at 22.5 dBm output power and 19.4% PAE. Experiments show 5-Gb/s BPSK, and simultaneous 2-Gb/s BPSK and 2-Gb/s ASK modulation per DAC cell in the 44–48 GHz range. Eye diagrams at 28 Gb/s further demonstrate the broadband operation of the DAC cell and its suitability as a large-swing NRZ modulator driver in fiberoptic links.

Scaling of SiGe BiCMOS Technologies for Applications above 100 GHz

This paper summarizes the technological developments carried out in STMicroelectronics to raise the fT / fMAX of SiGe HBTs up to ~ 300 GHz / 400 GHz. The noise and power performance in the W-band of different SiGe HBT generations are compared along with CML ring oscillators and circuit results up to the D band.

W-band 65-nm CMOS and SiGe BiCMOS transmitter and receiver with lumped I-Q phase shifters

This paper describes 80–94 GHz and 70–77 GHz I-Q phase shifters and the corresponding transmitter and receiver ICs, fabricated in 65-nm CMOS and SiGe BiCMOS technologies, respectively. Lumped inductors and transformers are employed to realize small-form factor 90° hybrids as needed in high density phased arrays. The CMOS transmitter operates with a saturated output power of +3 dBm and exhibits maximum absolute phase and amplitude errors of 14° and 5.5 dB, respectively, when the phase is varied from 0° to 360° in steps of 22.5°. The absolute phase error in the SiGe BiCMOS receiver is less than 8°, with a maximum gain imbalance below 3 dB over its 3-dB bandwidth of 70–77 GHz. The peak gain and power consumption are 3.8 dB and 142 mW from 1.2V supply for the CMOS transmitter, and 17 dB and 128 mW from 1.5V and 2.5V supplies for the SiGe BiCMOS receiver.

On-wafer s-parameter de-embedding of silicon active and passive devices up to 170 GHz

This paper compares for the first time open-short, split-through, and TRL de-embedding techniques for on-wafer characterization of silicon active and passive devices in the DC to 170 GHz range. It is demonstrated using transformers, capacitors, 65 nm MOSFETs and SiGe HBTs that, if the open and short dummies are designed to remain lumped through 170GHz, there is almost no difference between the three de-embedding techniques. For transistor test structures with series ground inductance, a new TRL + short de-embedding method is proposed.

A 45nm SOI CMOS Class-D mm-Wave PA with >10V pp differential swing

The ever-increasing demand for low-cost portable communication devices pushes for higher integration of wireless transceivers in deeply-scaled silicon technologies. Given the overwhelming digital content of a mobile platform, ideally, the RF components should be realized with topologies that allow for their seamless scaling into 22nm and 14nm CMOS technologies. The Power Amplifier (PA) remains one of the most challenging circuit blocks to implement in nanoscale CMOS due to the strict requirements for output power, efficiency and linearity imposed by wireless communication standards. The low breakdown voltage of nanoscale MOSFETs limits the maximum drain voltage swing and the maximum achievable output power. In order to circumvent this problem, a typical approach is to increase the device size and use a reactive matching network to transform the load resistance to a value significantly lower than 50Ω. Nevertheless, due to the typically low-Q passive components that can be manufactured in a nanoscale CMOS process, and because of the high impedance transformation ratio involved, most of the additional output power that would be gained by increasing the device size is wasted in resistive losses in the matching networks, resulting in poor efficiency. This problem is exacerbated at mm-Wave frequencies where the loss of the passive components is even higher, and using lower fT/fMAX thicker oxide or extended drain MOS devices [1] is not viable.

Second generation transceivers for D-band radar and data communication applications

A single chip, dual-functionality radio and FMCW radar transceiver, operating at 140 GHz is described. Doppler, loop-back, and 4Gb/s NLOS radio link demos, over the air and at distances exceeding one meter, are demonstrated. The second part of the paper presents novel, sub-1.8 V circuit topologies intended for a low power, high resolution 120 GHz radar transceiver with self-calibration capabilities. The measured receiver noise figure, gain, and phase noise are 7.5 dB, 20 dB, and −100 dBc/Hz@1MHz offset, respectively.

Device and IC Characterization Above 100 GHz

Due to the aggressive scaling of metal-oxide-semiconductor field-effect transistors (MOSFETs) and silicon germanium SiGe heterojunction bipolar transistors (HBTs), silicon-based circuits operating above 100 GHz are becoming a reality. However, at present, most, if not all semiconductor foundries extract their transistor and passive device models from measurements conducted below 110 GHz and often below 65 GHz. In order to reduce the number of design iterations, accurate S-parameter characterization techniques above 100 GHz are required for active and passive devices such that compact models may be developed and verified on representative circuits.

Characterization and Modeling of an SiGe HBT Technology for Transceiver Applications in the 100–300-GHz Range

This paper describes a methodology for extracting and verifying the high-frequency model parameters of the HICUM L0 and L2 models of a silicon-germanium HBT from device and circuit measurements in the 110-325-GHz range. For the first time, the non-quasi-static effects, missing in the HICUM/L0 model, are found to be essential in accurately capturing the frequency dependence of the transistor maximum available power gain beyond the inflection frequency for unconditional stability. Furthermore, it is demonstrated that the optimal partitioning of the area and periphery components of the junction base-emitter, base-collector, and collector-substrate capacitances, and of the internal and external base and collector resistances can only be determined from S -parameter measurements beyond 200 GHz. The extracted models are validated on state-of-the-art linear and nonlinear circuits (amplifier, voltage-controlled oscillator (VCO), and VCO + divider chain) operating at frequencies as high as 240 GHz.