Irfan M. Ovacik

Decomposition methods for complex factory scheduling problems

Preface. 1. Introduction. 2. Industrial Context and Motivation for Decomposition Methods. 3. Review of Decomposition Methods for Factory Scheduling Problems. 4. Modelling Interactions Between Subproblems: The Disjunctive Graph Representation and Extensions. 5. Workcenter-Based Decomposition Procedures for the Classical Job Shop Environment. 6. A Generic Decomposition Procedure for Semiconductor Testing Facilities. 7. Time-Based Decomposition Procedures for Single-Machine Subproblems with Sequence-Dependent Setup Times. 8. Time-Based Decomposition Procedures for Parallel Machine Subproblems with Sequence-Dependent Setup Times. 9. Naive Rolling Horizon Procedures for Job Shop Scheduling. 10. Tailored Decomposition Procedures for Semiconductor Testing Facilities. 11. Computational Results for Job Shops with Single and Parallel Machine Workcenters. 12. The Effects of Subproblem Solution Procedures and Control Structures. 13. Conclusions and Future Directions. Author Index.

Exploiting shop floor status information to schedule complex job shops

Abstract We propose a heuristic for scheduling complex job shops that uses the shop floor status information available in many of todays computerized systems to make dispatching decisions. We describe four variants of this procedure and evaluate their performance in three different shop configurations: a job shop with random routings, a reentrant flow shop, and a semiconductor testing facility. Results show that the algorithms perform better than dispatching rules with modest increases in computation time. The amount of improvement obtained depends on the shop configuration, with substantial improvements being obtained for the semiconductor testing facility and reentrant flow shops.

Decomposition methods for scheduling semiconductor testing facilities

We present decomposition procedures for scheduling semiconductor testing facilities. These facilities are characterized by the presence of different types of work centers, some of which have sequence-dependent setup times and some parallel identical machines. We exploit the structure of the routings in semiconductor testing to develop tailored decomposition procedures that decompose the shop into a number of work centers that are scheduled using specialized procedures. Extensive computational experiments show that these procedures significantly outperform existing methods in reasonable CPU times. These results indicate that decomposition methods can be successfully applied to complex scheduling problems of the type addressed in this paper, as well as the classical job shop problems addressed in previous research.

A shifting bottleneck algorithm for scheduling semiconductor testing operations

In this paper we present a shifting bottleneck algorithm for scheduling semiconductor testing operations. The algorithm uses global information on the entire state of the shopfloor and a workcenter-based decomposition approach. Workcenters are scheduled one at a time in order of decreasing criticality until a schedule for the entire shop has been developed. The interactions between workcenters are captured using a disjunctive graph representation of the problem. We describe an implementation of two variants of this procedure and compare their performance against that of a number of dispatching rules. Our results show that one of the shifting bottleneck algorithms performs significantly better than all the dispatching rules within reasonable computation times.

Performance evaluation of dispatching rules for semiconductor testing operations

We evaluate the performance of several dispatching rules in a semiconductor testing environment and examine the effects of uncertainties in problem data and job arrival patterns. A series of simulation experiments shows that a single dispatching rule seldom performs well for several different performance measures simultaneously, non-homogenous job arrival patterns significantly affect several aspects of system performance while uncertainty in problem data does not, and the choice of dispatching rules for a given performance measure is robust to both arrival patterns and uncertainties.

Worst-case error bounds for parallel machine scheduling problems with bounded sequence-dependent setup times

We consider minimizing makespan (Cmax) and maximum lateness (Lmax) on parallel identical machines with sequence-dependent setup times. We show that the optimal schedule need not be a list schedule. Motivated by a practical scheduling problem, we study the class of problems where setup times are bounded by processing times and develop tight worst case error bounds for list scheduling algorithms to minimize Cmax and Lmax.

Integrating Interval Estimates of Global Optima and Local Search Methods for Combinatorial Optimization Problems

The problem of estimating the global optimal values of intractable combinatorial optimization problems is of interest to researchers developing and evaluating heuristics for these problems. In this paper we present a method for combining statistical optimum prediction techniques with local search methods such as simulated annealing and tabu search and illustrate the approach on a single machine scheduling problem. Computational experiments show that the approach yields useful estimates of optimal values with very reasonable computational effort.

Dispatching Rules For Semiconductor Testing Operations: A Computational Study

In this paper we compare the performance of different dispatching rules in a semiconductor testing environment for a variety of due-date and cycle time related performance measures. We also examine the effect of different models of job arrivals and uncertainties in the problem data on the performance of the dispatching rules. Our results indicate that no one rule performs well for all performance measures, and that performanceis robust to uncertainties and non-homogeneity in the arrival process.

A Generic Decomposition Procedure for Semiconductor Testing Facilities

The previous chapters have outlined the industrial scheduling problems for which we wish to develop scheduling algorithms, the advantages of decomposition algorithms for these problems and a review of decomposition methods that have been developed for various scheduling problems in the past. In particular, Chapter 5 discussed workcenter-based decomposition algorithms for the job shop environment without sequence-dependent setup times. These approaches are generic in that they do not exploit special structure in the routings or other aspects of the problem.

Time-Based Decomposition Procedures for Single-Machine Subproblems

The main goal of this research, as discussed in Chapter 2, is to develop effective decomposition procedures to minimize Lmax in complex job shops of the type encountered in semiconductor testing and wafer fabrication facilities. In the workcenter-based approach we have followed, a key subproblem is that of minimizing Lmax on a workcenter consisting of a single machine, or parallel identical machines, in the presence of sequence-dependent setup times. These problems are strongly NP-hard, and are thus of considerable interest in their own right, apart from their importance in developing effective decomposition procedures for the overall job shop problem. Experiments with generic decomposition procedures in Chapters 5 and 6 have shown that the quality of the subproblem solutions has a significant effect on the quality of the solution obtained for the overall problem. Hence it is desirable to develop heuristics that generate higher-quality solutions in reasonable computation times.