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Dive into the research topics where Iriya Muneta is active.

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Featured researches published by Iriya Muneta.


Applied Physics Express | 2017

Quantitative relationship between sputter-deposited-MoS2 properties and underlying-SiO2 surface roughness

Takumi Ohashi; Iriya Muneta; Kentaro Matsuura; Seiya Ishihara; Yusuke Hibino; Naomi Sawamoto; Kuniyuki Kakushima; Kazuo Tsutsui; Atsushi Ogura; Hitoshi Wakabayashi

Substrate roughness affects the physical and electrical properties of deposited layered materials. However, the quantitative relationship is unknown. In this work, a quantitative analysis of sputter-deposited MoS2 films on an SiO2 substrate was conducted. Flattening the substrate helped realize an MoS2 structure closer to the ideal honeycomb structure and a Hall mobility of ~26 cm2/(Vs) and a carrier density of ~1016 cm−3 (less than that of exfoliated MoS2 by 104). These results stress the necessity of considering even roughness of the order of angstroms to improve the physical and electrical properties of atomically layered functional devices.


international workshop on junction technology | 2017

Formation of Mo 2 C electrodes using stacked sputtering process for thermally stable SiC Schottky barrier diodes

Kuniyuki Kakushima; Tomoyuki Suzuki; Takuya Hoshii; Iriya Muneta; Hitoshi Wakabayashi; Kazuo Tsutsui; Hiroshi Iwai; Hiroshi Nohira

The introduction of SiC Schottky barrier diodes has enabled further power loss reduction in high voltage power electronics, owing to its high operation speed [1]. Various electrode materials for diodes have been reported so far, including Mo, Ti and Ni [2]. However, interface reactions between these metals and SiC surfaces results in the formation of an inhomogeneous interface, which rises concerns to long-term reliability issues. Mo2C electrodes, on the other hand, have revealed stable diode characteristics against an annealing up to 1050 °C, suggesting practically reliable operations in power electronics [3]. Although nice electrical characteristics were obtained, the physical analyses of the interface are still yet to be done. In this presentation, detailed analyses of the formation of a Mo2C layer on SiC surfaces using stacked sputtering process are reported [4].


international workshop on junction technology | 2017

Low temperature ohmic contact for p-type GaN using Mg electrodes

Kuniyuki Kakushima; Yuta Ikeuchi; Takuya Hoshii; Iriya Muneta; Hitoshi Wakabayashi; Kazuo Tsutsui; Hiroshi Iwai; T. Kikuchi; S. Ishikawa

Low Ohmic contact for p-type GaN (pGaN) has been of great importance for various applications including light emitting diodes and nitride based power devices. Although a low contact resistance (ρc) of the order of 10−6 Ωcm2 can be obtained with air-annealed Au/Ni electrodes, the hole transport relies on NiO islands inhomogeneously formed between the Au and the pGaN surface, giving concerns in long term reliability [1]. For Ti-based electrodes, on the other hand, an Ohmic contact can be achieved by forming an intermixed layer at the interface of the metal and pGaN surface, yet a relatively high temperature is required. Moreover, the ρc is reported to degrade along with time due to in-diffusion of hydrogen atoms stored in the metal layer during the high temperature annealing [2].


international workshop on junction technology | 2017

Resistivity reduction of low-carrier-density sputtered-MoS 2 film using fluorine gas

Yasunori Okada; Shimpei Yamaguchi; Takumi Ohashi; Iriya Muneta; Kuniyuki Kasushima; Kazuo Tsutsui; Hitoshi Wakabayashi

High-performance and low-power LSIs have been achieved by 3D transistor such as FinFET in logic and DRAM using crystalline-silicon channel and 3D-stacked devices in NAND flash using poly-crystalline-silicon channel [1]. For the future, monolithic transistors using atomic-layer materials are expected above the silicon devices [2]. A transition-metal di-chalcogenide (TMDC) such as molybdenum di-sulfide (MoS2) is one of the promising candidates because of not only a higher mobility but also attractive functionalities such as flexibility and transparency [3]. However, it is very difficult to reduce a contact resistance, especially using doping [4-7].


international conference on asic | 2017

3D scaling for insulated gate bipolar transistors (IGBTs) with low V ce(sat)

Kazuo Tsutsui; Kuniyuki Kakushima; Takuya Hoshii; Akira Nakajima; Shin Ichi Nishizawa; Hitoshi Wakabayashi; Iriya Muneta; Kumiko Sato; Tomoko Matsudai; Wataru Saito; Takuya Saraya; K. Itou; Munetoshi Fukui; Shinsuke Suzuki; Masaharu Kobayashi; Toshihiko Takakura; Toshiro Hiramoto; Atsushi Ogura; Y. Numasawa; Ichiro Omura; Hiromichi Ohashi; Hiroshi Iwai

Three dimensionally (3D) scaled IGBTs that have a scaling factor of 3 (k=3) with respect to current commercial products (k=1) were fabricated for the first time. The scaling was applied to the lateral and vertical dimensions as well as the gate voltage. A significant decrease in ON resistance, — Vce(sat) reduction from 1.70 to 1.26 V — was experimentally confirmed for the 3D scaled IGBTs.


ieee electron devices technology and manufacturing conference | 2017

Low-carrier density sputtered-MoS 2 film by H 2 S annealing for normally-off accumulation-mode FET

Jun'ichi Shimizu; Takumi Ohashi; Kentaro Matsuura; Iriya Muneta; Kuniyuki Kakushima; Kazuo Tsutsui; Nobuyuki Ikarashi; Hitoshi Wakabayashi

We investigate low-temperature formation process of sputtered-MoS<inf>2</inf> film. The MoS2 film was formed by radio frequency (RF) sputtering. Then the sputtered-MoS<inf>2</inf> was annealed in H2S at from 200 to 400°C. We find that the hydrogen sulfur (H<inf>2</inf>S) annealing compensate for sulfur defects at low temperature significantly, resulting in a lower carrier density of 2–10<sup>16</sup> cm<sup>−3</sup>.


ieee electron devices technology and manufacturing conference | 2017

Crystallinity improvement using migration-enhancement methods for sputtered-MoS 2 films

Shin Ichi Hirano; Jun'ichi Shimizu; Kentaro Matsuura; Takumi Ohashi; Iriya Muneta; Kuniyuki Kakushima; Kazuo Tsutsui; Hitoshi Wakabayashi

We investigate crystallinity of sputtered MoS<inf>2</inf> films formed in various sputtering conditions to enhance the migration. We found that high substrate temperature, high radio frequency (RF) power and long throw were effective for crystallinity improvement of sputtered MoS2 films and in these conditions higher Hall-effect mobility of 12 cm<sup>2</sup>/V-s and lower carrier density of 10<sup>18</sup> cm<sup>−3</sup> were achieved.


international workshop on junction technology | 2018

Characterization of β-Ga 2 O 3 Schottky barrier diodes

T. Kaneko; Iriya Muneta; Takuya Hoshii; Hitoshi Wakabayashi; Kazuo Tsutsui; Hiroshi Iwai; Kuniyuki Kakushima


ieee electron devices technology and manufacturing conference | 2018

Chip-Level-Integrated n MISFETs with Sputter-Deposited-MoS 2 Thin Channel Passivated by Al 2 O 3 Film and TiN Top Gate

Kentaro Matsuura; Jun'ichi Shimizu; Mayato Toyama; Takumi Ohashi; Iriya Muneta; Seiya Ishihara; Kuniyuki Kakushima; Kazuo Tsutsui; Atsushi Ogura; Hitoshi Wakabayashi


ieee electron devices technology and manufacturing conference | 2018

Self-Heating-Effect-Free p/n-Stacked-NW on Bulk-FinFETs and 6T-SRAM Layout

Eisuke Anju; Iriya Muneta; Kuniyuki Kakushima; Kazuo Tsutsui; Hitoshi Wakabayashi

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Hitoshi Wakabayashi

Tokyo Institute of Technology

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Kazuo Tsutsui

Tokyo Institute of Technology

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Kuniyuki Kakushima

Tokyo Institute of Technology

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Takumi Ohashi

Tokyo Institute of Technology

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Takuya Hoshii

Tokyo Institute of Technology

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Kentaro Matsuura

Tokyo Institute of Technology

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Hiroshi Iwai

Tokyo Institute of Technology

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Jun'ichi Shimizu

Tokyo Institute of Technology

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Eisuke Anju

Tokyo Institute of Technology

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