Isabelle Ferain

Junctionless multigate field-effect transistor

This paper describes a metal-oxide-semiconductor MOS transistor concept in which there are no junctions. The channel doping is equal in concentration and type to the source and drain extension doping. The proposed device is a thin and narrow multigate field-effect transistor, which can be fully depleted and turned off by the gate. Since this device has no junctions, it has simpler fabrication process, less variability, and better electrical properties than classical MOS devices with source and drain PN junctions.

Multigate transistors as the future of classical metal-oxide-semiconductor field-effect transistors

For more than four decades, transistors have been shrinking exponentially in size, and therefore the number of transistors in a single microelectronic chip has been increasing exponentially. Such an increase in packing density was made possible by continually shrinking the metal–oxide–semiconductor field-effect transistor (MOSFET). In the current generation of transistors, the transistor dimensions have shrunk to such an extent that the electrical characteristics of the device can be markedly degraded, making it unlikely that the exponential decrease in transistor size can continue. Recently, however, a new generation of MOSFETs, called multigate transistors, has emerged, and this multigate geometry will allow the continuing enhancement of computer performance into the next decade.

High-Temperature Performance of Silicon Junctionless MOSFETs

This paper investigates the temperature dependence of the main electrical parameters of junctionless (JL) silicon nanowire transistors. Direct comparison is made to silicon nanowire (trigate) MOSFETs. Variation of parameters such as threshold voltage and on-off current characteristics is analyzed. The JL silicon nanowire FET has a lager variation of threshold voltage with temperature than the standard inversion- and accumulation-mode FETs. Unlike in classical devices, the drain current of JL FETs increases when temperature is increased.

Reduced electric field in junctionless transistors

The electric field perpendicular to the current flow is found to be significantly lower in junctionless transistors than in regular inversion-mode or accumulation-mode field-effect transistors. Since inversion channel mobility in metal-oxide-semionductor transistors is reduced by this electric field, the low field in junctionless transistor may give them an advantage in terms of current drive for nanometer-scale complementary metal-oxide semiconductor applications. This observation still applies when quantum confinement is present.

Junctionless Nanowire Transistor (JNT): Properties and design guidelines

Conduction mechanisms in junctionless nanowire transistors (gated resistors) are compared to inversion-mode and accumulation-mode MOS devices. The junctionless device uses bulk conduction instead of surface channel. The current drive is controlled by doping concentration and not by gate capacitance. The variation of threshold voltage with physical parameters and intrinsic device performance is analyzed. A scheme is proposed for the fabrication of the devices on bulk silicon.

Junctionless Multiple-Gate Transistors for Analog Applications

This paper presents the evaluation of the analog properties of nMOS junctionless (JL) multigate transistors, comparing their performance with those exhibited by inversion-mode (IM) trigate devices of similar dimensions. The study has been performed for devices operating in saturation as single-transistor amplifiers, and we have considered the dependence of the analog properties on fin width Wfin and temperature T. Furthermore, this paper aims at providing a physical insight into the analog parameters of JL transistors. For that, in addition to device characterization, 3-D device simulations were performed. It is shown that, depending on gate voltage, JL devices can present both larger Early voltage VEA and larger intrinsic voltage gain AV than IM devices of similar dimensions. In addition, VEA and AV are always improved in JL devices when the temperature is increased, whereas they present a maximum value around room temperature for IM transistors.

Low subthreshold slope in junctionless multigate transistors

The improvement of subthreshold slope due to impact ionization is compared between “standard” inversion-mode multigate silicon nanowire transistors and junctionless transistors. The length of the region over which impact ionization takes place, as well as the amplitude of the impact ionization rate are found to be larger in the junctionless devices, which reduces the drain voltage necessary to obtain a sharp subthreshold slope.

SOI gated resistor: CMOS without junctions

We report the fabrication of junctionless SOI MOSFETs. Such devices greatly simplify processing thermal budget and behave as regular multigate SOI transistors.

Mobility improvement in nanowire junctionless transistors by uniaxial strain

Improvement of current drive in n- and p-type silicon junctionless metal-oxide-semiconductor-field-effect-transistors (MOSFETs) using strain is demonstrated. Junctionless transistors have heavily doped channels with doping concentrations in excess of 10(19) cm(-3) and feature bulk conduction, as opposed to surface channel conduction. The extracted piezoresistance coefficients are in good agreement with the piezoresistive theory and the published coefficients for bulk silicon even for 10 nm thick silicon nanowires as narrow as 20 nm. These experimental results demonstrate the possibility of enhancing mobility in heavily doped silicon junctionless MOSFETs using strain technology

Improvement of carrier ballisticity in junctionless nanowire transistors

In this work we show that junctionless nanowire transistor (JNT) exhibits lower degree of ballisticity in subthreshold and higher ballisticity above threshold compare to conventional inversion-mode transistors, according to quantum mechanical simulations. The lower degradation of the ballisticity above threshold region gives the JNT near-ballistic transport performance and hence a high current drive. On the other hand, lower ballisticity in subthreshold region helps reducing the off-current and improves the subthreshold slope. A three-dimensional quantum mechanical device simulator based on the nonequilibrium Green’s function formalism in the uncoupled mode-space approach has been developed to extract the physical parameters of the devices.