Isael Diaz

A sign-bit auto-correlation architecture for fractional frequency offset estimation in OFDM

This paper presents an architecture of an autocorrelator for Orthogonal Frequency Division Multiplexing systems. The received signal is quantized to only the sign-bit, which dramatically simplifies the frequency offset estimation. Hardware cost is reduced under the assumption that synchronization during acquisition does not have to be very accurate, but sufficient for coarse estimation. The architecture is synthesized towards a 65nm low-leakage high threshold standard cell CMOS library. The proposed architecture results in area reduction of 93% if compared to typical 8-bit implementation. The area occupied by the architecture is 0.063 mm2. The architecture is evaluated for WLAN, LTE and DVB-H. Power simulations for DVB-H transmission shows a power consumption of 4.8µW per symbol.

Performance Analysis of Sign-Based Pre-FFT Synchronization in OFDM Systems

This paper treats the feasibility to use only the sign bit of the in-phase and quadrature components when estimating time and frequency in OFDM systems. Using only the sign bit is shown to result in a frequency dependent bias, which can be easily compensated. The approach is evaluated for LTE and DVB-H, when the estimation is performed using the cyclic prefix, and for WLAN 802.11g, when the estimation is done using the short training field (STF). The performance is compared to a floating point implementation, and it is also compared to what is believed to be reasonable requirements for initial time and frequency estimation.

A reconfigurable OFDM inner receiver implemented in the CAL dataflow language

This paper presents a reconfigurable inner receiver for the LTE, DVB-H, and IEEE802.11n (WLAN) radio systems, all of which are based on orthogonal frequency division multiplexing (OFDM). The receiver is implemented in the CAL language. An FPGA-based hardware implementation is synthesized from RTL generated from the CAL description. The purpose of our work is to investigate the feasibility of dataflow methodology for high-level description of digital radio transceivers.

Analysis of a novel low complex SNR estimation technique for OFDM systems

Signal-to-noise ratio (SNR) estimation is commonly used in wireless receivers to enhance the performance in different ways. In this paper a novel low complexity SNR estimator for OFDM is proposed. The estimator might be implemented using floating point representation or by using only the sign-bit, and can if desired be effectively implemented by reconfiguring the standard correlator used for time- and frequency estimation. Closed form expressions for the SNR estimate are derived for both the floating point implementation and the sign-bit implementation, and compared to simulation results both for an additive white Gaussian noise (AWGN) channel and for a frequency selective channel showing the feasibility of the proposed algorithm.

Sign-bit based architecture for OFDM Acquisition for multiple-standards

This paper presents a hardware mapping of an auto-correlator for Orthogonal Frequency Division Multiplexing stage for three radio standards: LTE, DVB-H, and IEEE 802.11n. Hardware cost is minimized by using only the sign bit in the autocorrelation function. The frequency offset estimation procedure is dramatically simplified by reducing the phase of the envelope to ¿/2 resolution, which in turn reduces the need of specialized components. The architecture is synthesized towards a 65 nm low-leakage high threshold standard cell CMOS library. The 1-bit architecture reports an area reduction of 90% for memories, 56% for the logic and a power dissipation reduction of 35%, when compared to an identical 8-bit implementation. The approximate area occupied by the architecture is 0.03 mm2. Power simulations for IEEE 802.11n packet reports a power dissipation of 42 ¿W.

Highly scalable implementation of a robust MMSE channel estimator for OFDM multi-standard environment

In this paper a VLSI implementation of a highly scalable MMSE (Minimum Mean Square Estimator) is presented with the ultimate goal of demonstrating the potential of MMSE as enabler for multi-standard channel estimation. By selecting an appropriate implementation, a complexity reduction of 98% is achieved when compared to Time-Domain Maximum Likelihood Estimation (TDMLE), whereas low power consumption is accomplished by implementing a low-power-mode. The architecture is capable of performing Least Square (LS) estimation and MMSE compliant with 3GPP LTE (Long Term Evolution), IEEE 802.11n (WLAN), and DVB-H (Digital Video Broadcast for Handheld Devices), The estimator is synthesized using a 65nm low-leakage high-threshold standard-cell CMOS library. The design occupies an area of 0.169 mm2, is capable of running upto 250 MHz, providing a throughput of 78M estimates/second. Simulations under a typical LTE reception show that the implementation dissipates 4.9μW per sample.

Reconfigurable cell array for concurrent support of multiple radio standards by flexible mapping

This paper presents a flexible architecture suitable for concurrent processing of multiple radio standards. The proposed architecture is based on a coarse-grained reconfigurable cell array, consisting of distinct processing and memory cells. Flexibility of the architecture is demonstrated by performing a coarse time synchronization and fractional frequency offset estimation for multiple OFDM standards. The radio standards under analysis are IEEE 802.11n, LTE, and DVB-H. The reconfigurable cell array, containing 2-by-2 cells, is capable of processing two concurrent data streams from the standards. Dynamic reconfigurability of the architecture enables run-time switching between the standards. The implemented 2-by-2 cell array is synthesized using a 65 nm low-leakage standard cell CMOS library, resulting in an area of 0.479mm2 and a maximum clock frequency of 534MHz. High flexibility offered by the reconfigurable cell array allows the adoption of different algorithms onto the same platform.

Nex generation digital front-end for multi-standard concurrent reception

This article presents an architecture of a Digital Front-End Receiver (DFE-Rx) for the next-generation mobile terminals. A main focus is placed in flexibility, scalability and concurrency. The architecture is capable of detecting, synchronizing and reporting carrier-frequency offset, of multiple concurrent radio standards. The proposed receiver is fabricated in a 65 nm CMOS low power high-VT cell technology in a die size of 5mm2. The synchronization engine has been measured at 1.2V and reports an average power consumption of 1.9mW during IEEE 802.11 (WLAN) reception and 1.6mW during configuration, while running at 10 MHz.

A 350μW Sign-Bit architecture for multi-parameter estimation during OFDM acquisition in 65nm CMOS

Correct estimation of symbol timing, Carrier Frequency Offset (CFO), and Signal-to-Noise Ratio (SNR) is crucial in Orthogonal Frequency Division Multiplexing (OFDM) communication. Typically, high estimation accuracy is desired, but often comes with increased complexity. Which has a direct repercussion in energy consumption. In this article, an architecture based on Sign-Bit estimation with low complexity, and hence low power dissipation, is presented. The architecture, is capable of estimating the afore-mentioned parameters in virtually any OFDM standard. The proof of concept has been fabricated in 65nm CMOS technology with low-power high-VT cells. Measurements performed with supply voltage of 1.2V. resulted in a power dissipation of 350 μW, 6 times smaller to that of an equivalent 8-bit architecture, and the lowest power density reported in literature.

A new digital front-end for flexible reception in software defined radio

Future mobile terminals are expected to support an ever increasing number of Radio Access Technologies (RAT) concurrently. This imposes a challenge to terminal designers already today. Software Defined Radio (SDR) solutions are a compelling alternative to address this issue in the digital baseband, given its high flexibility and low Non-Recurring Engineering (NRE) cost. However, the challenge still remains in the Digital Front-End (DFE), where many operations are too complex or energy hungry to be implemented as software instructions. Thus, new architectures are needed to feed the SDR digital baseband while keeping complexity and energy consumption at bay. In this article the architecture of a Digital Front-End Receiver (DFE-Rx) for the next-generation mobile terminals is presented. The flexibility needed for multi-standard support is demonstrated by detecting, synchronizing and reporting carrier-frequency offset, of multiple concurrent radio standards. Moreover, the proposed architecture has been fabricated in a 65nm CMOS low power high-VT cell technology in a die size of 5mm2. The core module of the DFE-Rx, the synchronization engine, has been measured at 1.2V and reports an average power consumption of 1.9mW during Wireless Local Area Network (WLAN) reception and 1.6mW during configuration, while running at 10MHz.