Isao Takayanagi

8.9-Megapixel Video Image Sensor With 14-b Column-Parallel SA-ADC

An 8.9-megapixel 60-frames/s video image sensor with a 14-b column-parallel analog-to-digital converter (ADC) has been developed. A gain amplifier, a 14-b successive approximation ADC (SA-ADC), and a new column digital processor are employed in each column. The SA-ADC has sufficient operation speed to convert the pixel reset and the pixel signal into digital data in a row operation cycle. The column digital processor receives bit serial data from the SA-ADC output and performs subtraction of the reset data from the signal data in order to reduce column fixed pattern noise (FPN). Column FPN is successfully reduced to 0.36 erms - by this digital-domain column FPN correction. Low-voltage low-power serial video interface and noise decoupling on pixel drive voltages contribute to row-temporal-noise reduction to 0.31 erms -. Both column FPN and row temporal noise are not visible in spite of a low readout noise floor of 2.8 erms -.

The operation mechanism of a charge modulation device (CMD) image sensor

The operational mechanism of the charge modulation device (CMD) as an image sensor is presented. A newly developed device simulator, the transistor analysis program for imagers calculating non-steady-state equations (TRINE) is used in this analysis. Comparison of the calculated results with measured data shows that the model predictions are consistent with measured electrical and optical characteristics within a range of 20%. The operational mechanism has been clarified, and the accuracy of the method proves that it is effective in quantitative device design. The discretization scheme of the cylindrical coordinate system used is also shown. >

A 1.25-inch 60-frames/s 8.3-M-pixel digital-output CMOS image sensor

The ultrahigh-definition television (UDTV) camera system requires an image sensor having four times higher resolution and two times higher frame rate than the conventional HDTV systems. Also, an image sensor with a small optical format and low power consumption is required for practical UDTV camera systems. To respond to these requirements, we have developed an 8.3-M-pixel digital-output CMOS active pixel sensor (APS) for the UDTV application. It features an optical format of 1.25inch, low power consumption of less than 600 mW at dark, while reproducing a low-noise, 60-frames/s progressive scan image. The image sensor is equipped with 1920 on-chip 10-bit analog-to-digital converters and outputs digital data stream through 16 parallel output ports. Design considerations to reproduce a low-noise, high-resolution image at high frame rate of 60 fps are described. Implementation and experimental results of the 8.3-M-pixel CMOS APS are presented.

A 1 1/4 inch 8.3M pixel digital output CMOS APS for UDTV application

A 3936/spl times/2196 pixel CMOS APS has a 10 b column-based ADC. It operates at 49.5 MHz in a progressive scanning mode at 60 frames/s and achieves a 2000 TV line resolution, sensitivity of 4200 b/lux-s, and power consumption of less than 760 mW.

A very low column FPN and row temporal noise 8.9 M-pixel, 60 fps CMOS image sensor with 14bit column parallel SA- ADC

A 1.25-inch optical format, 8.9 M-pixel CMOS image sensor that employs a 4T pinned photodiode (P-PD) pixel and 14 bit column ADCs is reported. A 14 bit or 12 bit digital video signal is streamed out via 16-lane low-voltage, low-power differential serial output ports in 50 fps and 60 fps operations, respectively. Temporal noise floor of 2.8^- _rms and linear full-well of 27.8ke^- were obtained at 60 fps operation. Row temporal noise and column FPN are as small as 0.31 e^- _rmsrms and 0.36 e^- _rms, respectively.

Dark current reduction in stacked-type CMOS-APS for charged particle imaging

A stacked CMOS-active pixel sensor (APS) with a newly devised pixel structure for charged particle detection has been developed. At low operation temperatures (<200 K), the dark current of the CMOS-APS is determined by the hot carrier effect. A twin well CMOS pixel with a p-MOS readout and n-MOS reset circuit achieves low leakage current as low as 5/spl times/10/sup -8/ V/s at the pixel electrode under liquid nitrogen temperature of 77 K. The total read noise floor of 0.1 mV/sub rms/ at the pixel electrode was obtained by nondestructive readout correlated double sampling (CDS) with the CDS interval of 21 s.

Measurement of electron impact ionization coefficient in bulk silicon under a low-electric field

The electron impact ionization coefficient, α n , in bulk silicon, was extracted using a new method that is applicable for the low‐electric fields. In this method, α n can be simply estimated from the multiplication factor of an n‐type static induction transistor, and a structurally determined depletion layer thickness. Values of α n , as low as 1×10−4 cm−1, have been obtained at 300 and 77 K, and they agreed approximately with previously reported data that covered relatively high electric fields.

A 250 k-pixel SIT image sensor operating in its high-sensitivity mode

A solid-state imaging device which uses a static induction transistor (SIT) is examined. The image sensor consists of 530(H)*490(V) pixels and is suitable for a 2/3-in optical format. An analysis of its operation predicts that the performance of the image sensor can be examined in detail using an equivalent circuit. A noise equivalent irradiance of 1.5*10/sup -4/ mu W/cm/sup 2/, when using light-emitting diodes ( lambda =660 nm) as a light source, was obtained in a frame integration mode. This is comparable to that of a high-sensitivity silicon intensifier target tube, although a large image lag of 80% during the third frame is also present. High sensitivity, is achieved because the gate reset levels of the SIT depend on the exposure and the change of the gate reset levels added to the output signal. It is predicted that the image sensor will be highly sensitive but that it will have a large image lag. >

Analysis of operational speed and scaling down the pixel size of a charge modulation device (CMD) image sensor

In a previous paper, the authors (ibid., vol.38, pp.989-998, May 1991) clarified the operational mechanism of a charge modulation device (CMD) image sensor and confirmed that numerical calculations using the transistor analysis program for imagers calculating non-steady-state equations (TRINE) predicted the actual performance of a CMD imager within a 20% discrepancy. Following these results, the scaling-down of device dimensions and the inherent operational speed are estimated using TRINE in order to realize a future high-resolution CMD image sensor. The analysis shows that a device size of 5.0 mu m (H)*5.2 mu m (V) is attainable without degrading the performance of the 10.2 mu m (H)*10.4 mu m (V) CMD imager and that the operational speed of a CMD is fast enough for a high-definition TV (HDTV) application which requires a scan rate of several tens of nanoseconds. >

High-Resolution CMOS Video Image Sensors

High-definition television (HDTV) images are now commonly available and the recent trend of video applications is toward even higher spatial resolutions with higher pixel rates. To make such high-resolution video images possible, the sensor must have a line time, or one row time, of less than a few microseconds with a pixel rate greater than gigapixels per second. In this paper, the basics of complementary metal-oxide-semiconductor (CMOS) image sensors and the architectures/technologies used to obtain such high resolutions and frame rates are reviewed and the technologies to obtain the highest possible quality video images are explained.