Issam Damaj

Parallel algorithms development for programmable devices with application from cryptography

Reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs), have been witnessing a considerable increase in density. State-of-the-art FPGAs are complex hybrid devices that contain up to several millions of gates. Recently, research effort has been going into higher-level parallelization and hardware synthesis methodologies that can exploit such a programmable technology. In this paper, we explore the effectiveness of one such formal methodology in the design of parallel versions of the Serpent cryptographic algorithm. The suggested methodology adopts a functional programming notation for specifying algorithms and for reasoning about them. The specifications are realized through the use of a combination of function decomposition strategies, data refinement techniques, and off-the-shelf refinements based upon higher-order functions. The refinements are inspired by the operators of Communicating Sequential Processes and map easily to programs in Handel-C (a hardware description language). In the presented research, we obtain several parallel Serpent implementations with different performance characteristics. The developed designs are tested under Celoxica’s RC-1000 reconfigurable computer with its two million gates Virtex-EFPGA. Performance analysis and evaluation of these implementations are included.

Parallel algorithms development for programmable logic devices

Programmable logic devices (PLDs) continue to grow in size and currently contain several millions of gates. At the same time, research effort is going into higher-level hardware synthesis methodologies for reconfigurable computing that can exploit PLD technology. In this paper, we explore the effectiveness and extend one such formal methodology in the design of massively parallel algorithms. We take a step-wise refinement approach to the development of correct reconfigurable hardware circuits from formal specifications. A functional programming notation is used for specifying algorithms and for reasoning about them. The specifications are realised through the use of a combination of function decomposition strategies, data refinement techniques, and off-the-shelf refinements based upon higher-order functions. The off-the-shelf refinements are inspired by the operators of communicating sequential processes (CSP) and map easily to programs in Handel-C (a hardware description language). The Handel-C descriptions are directly compiled into reconfigurable hardware. The practical realisation of this methodology is evidenced by a case studying the matrix multiplication algorithm as it is relatively simple and well known. In this paper, we obtain several hardware implementations with different performance characteristics by applying different refinements to the algorithm. The developed designs are compiled and tested under Celoxicas RC-1000 reconfigurable computer with its 2 million gates Virtex-E FPGA. Performance analysis and evaluation of these implementations are included.

Performance analysis of extended vector-scalar operations using reconfigurable computing

This paper maps a new application, namely vector-scalar operations, onto the M1 MorphoSys (from UCI) reconfigurable computing system. A performance analysis study of the M1 RC is also presented to evaluate the efficiency of the algorithm execution on the M1 system. For instance, two algorithms on an 8/spl times/8 RC array M1 were run, and numerical examples were simulated to validate our results, using the MorphoSys mULATE program, which simulates MorphoSys operation.

Advances in industrial engineering and operations research

A Comprehensive Movement Compatibility Study for Hong Kong Chinese.- A Study of Comparative Design Satisfaction Between Culture and Modern Bamboo Chair.- Factors Influencing Symbol-Training Effectiveness.- Multiple-Colony Ant Algorithm with Forward-Backward Scheduling Approach for Job-Shop Scheduling Problem.- Proposal of New Paradigm for Hand and Foot Controls in the Context of Spatial Compatibility Effect.- Development of a Mathematical Model for Process with S-Type Quality Characteristics to a Quality Selection Problem.- Temporal Aggregation and the Production Smoothing Model: Evidence from Electronic Parts and Components Manufacturing in Taiwan.- Simulations of Gear Shaving and the Tooth Contact Analysis.- On Aggregative Methods of Supplier Assessment.- Human Factors and Ergonomics for Nondestructive Testing.- A Novel Matrix Approach to Determine Makespan for Zero-Wait Batch Processes.- Interactive Meta-Goal Programming: A Decision Analysis Approach for Collaborative Manufacturing.- Nonlinear Programming Based on Particle Swarm Optimization.- A Heuristic for the Capacitated Single Allocation Hub Location Problem.- Multimodal Transport: A Framework for Analysis.- Fractional Matchings of Graphs.- Correlation Functions for Dynamic Load Balancing of Cycle Shops.- Neural Network-Based Integral Sliding Mode Control for Nonlinear Uncertain Systems.- Decentralized Neuro-Fuzzy Control of a Class of Nonlinear Systems.- A New Training Algorithm of Adaptive Fuzzy Control for Chaotic Dynamic Systems.- General-Purpose Simulation Management for Satellite Navigation Signal Simulation.- Multilayered Quality-of-Service Architecture with Cross-layer Coordination for Teleoperation System.- Improvement of State Estimation for Systems with Chaotic Noise.- Combined Sensitivity-Complementary Sensitivity Min-Max Approach for Load Disturbance-Setpoint Trade-off Design.- Nonlinear Adaptive Sliding Mode Control for a Rotary Inverted Pendulum.- Robust Load Frequency Sliding Mode Control Based on Uncertainty and Disturbance Estimator.- Robust Intelligent Motion Control for Linear Piezoelectric Ceramic Motor System Using Self-constructing Neural Network.- Development of Hybrid Magnetic Bearings System for Axial-Flow Blood Pump.- Critical Angle for Optimal Correlation Assignment to Control Memory and Computational Load Requirements in a Densely Populated Target Environment.- High-Precision Finite Difference Method Calculations of Electrostatic Potential.- Newton-Tau Method.- Reconfigurable Hardware Implementation of the Successive Overrelaxation Method.- Tabu Search Algorithm Based on Strategic Oscillation for Nonlinear Minimum Spanning Tree Problems.- Customization of Visual Lobe Measurement System for Testing the Effects of Foveal Load.

Serpent Cryptography on Static and Dynamic Reconfigurable Hardware

This paper presents parallel reconfigurable hardware implementations of the Serpent (AES Finalist) cryptographic algorithm. Currently, Serpent is well known to be a simple but very strong encryption algorithm. The use of such an algorithm within critical applications, such as banking and military, requires efficient and highly reliable hardware implementation. We will stress the affordability of such requirements by analyzing and evaluating parallel Serpent implementations using static and dynamic reconfigurable systems. The used systems are the MorphoSys dynamically reconfigurable computer and The RC-1000 statically reconfigurable system from Celoxica Ltd with its 2 million gates Xilinx Virtex-E FPGA. In this paper, different designs for the Serpent corresponding to different Degrees of parallelism are presented. Moreover, implementation, realization, and performance analysis and evaluation of the mapped designs are included.

High-speed KATAN ciphers on-a-chip

Security in embedded systems has become a main requirement in modern electronic devices. The demand for low-cost and highly secure cryptographic algorithms is increasingly growing in fields such as mobile telecommunications, handheld devices, etc. In this paper, we analyze and evaluate the development of cheap and relatively fast hardware implementations of the KATAN family of block ciphers. KATAN is a family of six hardware oriented block ciphers. All KATAN ciphers share an 80-bit key and have 32, 48, or 64-bit blocks. We use VHDL under Altera Quartus in conjunction with ModelSim to implement and analyze our hardware designs. The developed designs are mapped onto high-performance Field Programmable Gate Arrays. We compare our findings with similar hardware implementations and C software versions of the algorithms. The performance analysis of the C implementations is done using Intel Vtune Amplifier running on Dell precision T7500 with its dual quad-core Xeon processor and 24 GB of RAM. The obtained results show better performance when compared with existing hardware and software implementations.

Multigrid solvers in reconfigurable hardware

The problem of finding the solution of partial differential equations (PDEs) plays a central role in modeling real world problems. Over the past years, Multigrid solvers have showed their robustness over other techniques, due to its high convergence rate which is independent of the problem size. For this reason, many attempts for exploiting the inherent parallelism of Multigrid have been made to achieve the desired efficiency and scalability of the method. Yet, most efforts fail in this respect due to many factors (time, resources) governed by software implementations. In this paper, we present a hardware implementation of the V-cycle Multigrid method for finding the solution of a 2D-Poisson equation. We use Handel-C to implement our hardware design, which we map onto available field programmable gate arrays (FPGAs). We analyze the implementation performance using the FPGA vendors tools. We demonstrate the robustness of Multigrid over other similar iterative solvers, such as Jacobi and successive over relaxation (SOR), in both hardware and software. We compare our findings with a C++ version of each algorithm. The obtained results show better performance when compared to existing software versions.

A unified approach for assessing capstone design projects and student outcomes in computer engineering programs

A capstone design project is an extensive piece of work that requires creative activity and thinking. It provides a unique opportunity for students to demonstrate their abilities, skills, and experiences that are attained throughout a bachelor of engineering program. The learning outcomes of capstone projects mostly map to all student outcomes at the program level. This paper presents a unified assessment framework for capstone design courses which allows for sound evaluations of student performance and project qualities in addition to assessing student outcomes. The developed framework comprises criteria, indicators, extensive analytic rubrics, and a summative statistical formulation. The presented course and framework are supported by the results, analysis, and evaluation of a pilot study.

AgriSys: A smart and ubiquitous controlled-environment agriculture system

With new technological advancement in controlled-environment agriculture systems, the level of productivity has significantly increased. Agriculture systems are now more capable, reliable, and provide enhanced productivity. An agriculture environment can range from a single plant in a house, a backyard garden, a small farm, to a large farming facility. These agricultural automated systems will help in managing and maintain safe environment especially the agricultural areas. In this paper, we propose a smart Agriculture System (AgriSys) that can analyze an agriculture environment and intervene to maintain its adequacy. The system deals with general agriculture challenges, such as, temperature, humidity, pH, and nutrient support. In addition, the system deals with desert-specific challenges, such as, dust, infertile sandy soil, constant wind, very low humidity, and the extreme variations in diurnal and seasonal temperatures. The system interventions are mainly intended to maintain the adequacy of the agriculture environment. For a reduced controller complexity, the adoption of fuzzy control is considered. The system implementation relies on state-of-art computer interfacing tools from National Instruments as programmed under LabVIEW.

An analysis framework for hardware and software implementations with applications from cryptography

Abstract With the richness of present-day hardware architectures, tightening the synergy between hardware and software has attracted a great attention. The interest in unified approaches paved the way for newborn frameworks that target hardware and software co-design. This paper confirms that a unified statistical framework can successfully classify algorithms based on a combination of the heterogeneous characteristics of their hardware and software implementations. The proposed framework produces customizable indicators for any hybridization of processing systems and can be contextualized for any area of application. The framework is used to develop the Lightness Indicator System (LIS) as a case-study that targets a set of cryptographic algorithms that are known in the literature to be tiny and light. The LIS targets state-of-the-art multi-core processors and high-end Field Programmable Gate Arrays (FPGAs). The presented work includes a generic benchmark model that aids the clear presentation of the framework and extensive performance analysis and evaluation.