Itamar Levi

DPA-Secured Quasi-Adiabatic Logic (SQAL) for Low-Power Passive RFID Tags Employing S-Boxes

Low-power mobile devices such as RFID tags and WSNs that employ AES cryptographic modules are susceptible to differential power analysis (DPA) attacks. This paper presents a novel secured quasi-adiabatic logic (SQAL) technology that is both low-power and DPA immune. The efficiency of the SQAL technology was evaluated on an 8-bit AES-128 SBOX block and proved to be robust against DPA attacks. Compared to other adiabatic and non-adiabatic logic styles, the SQAL technology achieves better results in terms of power consumption and area overhead.

High speed Dual Mode Logic Carry Look Ahead Adder

A novel high speed Carry Look Ahead Adder (CLA) is presented. The proposed CLA is implemented using Dual Mode Logic (DML) methodology, as recently introduced by our group. DML allows dynamic switching between static and dynamic modes of operation. In static mode, the DML gates feature very low power dissipation with moderate performance, while in dynamic mode they achieve higher performance, albeit with increased power dissipation. The proposed CLA utilizes this powerful ability of DML by a dynamic selection of critical paths according to the input vectors. The chosen critical paths are operated in the dynamic mode and improve the CLA delay. The rest of the CLA operates in the DML static mode, improving CLA power consumption. A 32 bit DML CLA was designed in a 40nm low power TSMC process. Simulation results showed 45% gain in speed and 70% in power dissipation, when compared to the CMOS and dynamic CLAs, respectively.

Logical Effort for CMOS-Based Dual Mode Logic Gates

Recently, a novel dual mode logic (DML) family was proposed. This logic allows operation in two modes: 1) static and 2) dynamic modes. DML gates, which can be switched between these modes on-the-fly, feature very low power dissipation in the static mode and high performance in the dynamic mode. A basic DML gate is very simple and is composed of any static logic family gate and an additional clocked transistor. In this paper, we introduce the logical effort (LE) methodology for the CMOS-based DML family. The proposed methodology allows path length minimization, delay optimization, and delay estimation of DML logic. This is done by development of complete and approximated LE models, which allows easy extraction of design optimization parameters, such as optimum number of stages, gates sizing factors, and delay estimations. The proposed optimization is shown for the dynamic mode of operation. Theoretical mathematical analysis is presented, and efficiency of the proposed methodology is shown in a standard 40-nm CMOS process.

Dual Mode Logic—Design for Energy Efficiency and High Performance

The recently proposed dual mode logic (DML) gates family enables a very high level of energy-delay optimization flexibility at the gate level. In this paper, this flexibility is utilized to improve energy efficiency and performance of combinatorial circuits by manipulating their critical and noncritical paths. An approach that locates the designs critical paths and operates these paths in the boosted performance mode is proposed. The noncritical paths are operated in the low energy DML mode, which does not affect the performance of the design, but allows significant energy consumption reduction. The proposed approach is analyzed on a 128 bit carry skip adder. Simulations, carried out in a standard 40 nm digital CMOS process with , show that the proposed approach allows performance improvement of X2 along with reduction of energy consumption of X2.5, as compared with a standard CMOS implementation. At , improvements of 1.3X and 1.5X in performance and energy are achieved, respectively.

Data-Dependent Delays as a Barrier Against Power Attacks

Power analysis attacks utilize the correlation between the dissipated power and the processed data. Although the instantaneous power dissipation contains information it cannot be exploited without full reverse engineering. This article explores data-dependent instantaneous (intra-cycle) power dissipation and shows that it can be used as additional source of randomness that can be utilized as a barrier against power analysis attacks. Noiseless circuit simulations conducted on 65 nm standard CMOS and standard-cell-based dual-rail SBOXs show that large data-dependent variance in propagation delays enhance the immunity of the circuits.

Exploring back biasing opportunities in 28nm UTBB FD-SOI technology for subthreshold digital design

Ultra-Thin Body and Box Fully Depleted silicon on insulator (UTBB FD-SOI) has been identified as attractive technology that respond to market trends in mobile applications. Digital subthreshold design techniques allow to operate at the minimum energy point, thus leading to considerable energy savings. In this work, the impact of back biasing is analyzed for the subthreshold region with different threshold voltage device options. We show that back biasing is an effective knob to achieve the minimum energy point when either high or low performance is demanded. By applying forward back bias voltage of 1.5 V to low threshold voltage transistors we achieved a frequency boost by 8.23x while maintaining the same consumed energy per cycle. Using regular threshold voltage transistors reversed back biased by 1.5 V, the leakage current was reduced 13.5x. Furthermore, we show that a single p-well approach should be used when no back biasing is needed in the subthreshold regime.

A Low Energy and High Performance

A novel Dual Mode Square (DM2) adder is proposed. The DM2 adder achieves low energy, high performance and small area by combining two independent techniques recently proposed by the authors: dual-mode logic (DML) and dual-mode addition (DMADD). DML is a special gate topology that allows on-the-fly adaptation of the gates to real time system requirements, and also shows a wide energy-performance tradeoff. DMADD is probability based circuit architecture with a wide energy-performance tradeoff; however its utilization in a pipelined processor requires multi-cycle operation in some cases. We show how DML circuits avoid this requirement, and thus make it possible to transparently plug-in the DM2 adder and derive full benefits from the DMADD. Previous work showed that the DMADD can lead to energy savings of up to 50% at the same clock cycle, compared to conventional CMOS solutions. Simulation results in a 40 nm standard process shows that the proposed DM2 approach achieves additional energy savings of 27% to 36% for 64-bit and 32-bit adders, respectively, compared to DMADD.

{\rm DM}^{2}

First-order and high-order correlation-power-analysis attacks have been shown to be a severe threat to cryptographic devices. As such, they serve as a security measure for evaluation and comparison of security-oriented implementations. When properly designed, data-dependent delays can be used as a barrier to these attacks. This paper introduces a security-oriented delay assignment algorithm for mitigating single and multibit attacks. The algorithm enables a reduction of the correlation between the processed data and the consumed current by utilizing the data-dependent delays as a source of correlated noise. This is done while minimizing the area overhead, propagation time, and power. We show that for the same security level this new algorithm provides X2 and X6 more area efficiency, and X1.5 and X2.25 higher frequencies than a permuted path delay assignment and random embedding of delay elements.

Adder

Recently, we proposed a low-granularity back-bias control technique [1] optimized for the ultra-thin body and box (UTBB) fully-depleted silicon-on-insulator (FD-SOI) technology. The technique was preliminary evaluated through the design of a low-voltage 8-bit ripple carry adder (RCA), showing very competitive energy and delay values. In this paper, the characteristics of the low-granularity back-biasing control are explored considering as benchmarks basic logic gates as well as adders with different bit lengths. All the designed circuits were compared to their equivalent dynamic threshold voltage MOSFE T (DTMOS) and conventional CMOS designs. The higher efficiency of low granularity body bias control is emphasized by the single well layout strategy, offered by the 28 nm UTBB FD-SOI technology, thus leading our approach to achieve competitive silicon area occupancy along with significant performance and energy improvements. More precisely, postlayout simulations have demonstrated that circuits designed according the suggested strategy, can achieve a delay reduction of 33% compared to conventional CMOS designs, whereas the energy consumption can be reduced down to 46% compared to DTMOS solutions, for a supply voltage of 0.4V. These results were obtained while maintaining robustness against process and temperature variations.

CPA Secured Data-Dependent Delay-Assignment Methodology

Power analysis attacks have become one of the most significant security threats to modern cryptographic digital systems. In this paper, we introduce a new CMOS-based blurring gate (BG) which increases the immunity of a cryptographic system to these attacks. The BG switches randomly between two operational-modes, static and dynamic. When embedded in the crypto-core, the BGs enforce different and unpredictable arrival times (propagation delays) along the logic paths from inputs to outputs. This results in blurred power profiles and random propagation delays, which in turn mitigate power attacks. Simulation results and security analyses using system with embedded BG units with standard 65-nm technology, clearly show higher immunity to power analysis attacks over other standard-library based randomization technologies. The signal-to-noise ratio (SNR) decreases rapidly below 1 for a relatively small amount of BGs even with a large number of power traces in the worst case test environment.