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Itoh Kiyoo

Hitachi

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Archive | 1980

SPEICHERVORRICHTUNG MIT HOCHGESCHWINDIGKEITS-SPEICHERZELLENWAEHLEINRICHTUNG

Tanaka Hirotoshi; Kawajiri Yoshiki; Chiba Koutsu; Hori Ryoichi; Itoh Kiyoo

Archive | 1991

MONOLITHIC SEMICONDUCTOR MEMORY DECREASING RESISTANCE OF DATA LINE

Itoh Kiyoo; Hori Ryoichi

Archive | 1989

Semiconductor device with a memory circuit and an analog circuit

Hori Ryoichi; Itoh Kiyoo; Tabei Takashi

IEICE Technical Report; IEICE Tech. Rep. | 2012

Device-Conscious Circuit Designs for 0.5-V High-Speed Nanoscale CMOS LSIs

Kotabe Akira; Itoh Kiyoo; Takemura Riichiro; Tsuchiya Ryuta; Horiguchi Masashi

IEICE Technical Report; IEICE Tech. Rep. | 2011

Sense Amplifier with Current Control Switch for Small-sized 0.5-V Gigabit-DRAM Arrays

Kotabe Akira; Yanagawa Yoshimitsu; Takemura Riichiro; Sekiguchi Tomonori; Itoh Kiyoo

IEICE Technical Report; IEICE Tech. Rep. | 2005

A 0.4-V High-Speed Long-Retention-Time DRAM Array with 12 F2 Twin Cell

Takemura Riichiro; Itoh Kiyoo; Sekiguchi Tomonori; Akiyama Satoru; Hanzawa Satoru; Kajigaya Kazuhiko; Kawahara Takayuki

IEICE Technical Report; IEICE Tech. Rep. | 2004

Dynamic-Vth, Dual-Power-Supply SRAM Cell Using D2G-SOI for Low-Power SoC Application

Yamaoka Masanao; Osada Kenichi; Itoh Kiyoo; Tsuchiya Ryuta; Kawahara Takayuki

Archive | 2001

SEMICONDUCTOR DEVICE WITH INTERNAL POWER SUPPLY

Watanabe Takao; Hori Ryoichi; Kitsukawa Gorou; Kawajiri Yoshiki; Kawahara Takayuki; Itoh Kiyoo

Archive | 1993

HALBLEITEREINRICHTUNG MIT BIPOLAREM TRANSISTOR UND ISOLIERSCHICHT-FELDEFFEKTTRANSISTOR.

Watanabe Takao; Kitukawa Goro; Hori Ryoichi; Itoh Kiyoo; Kawajiri Yoshiki; Kawahara Takayuki

Archive | 1986

SEMICONDUCTOR DEVICE HAVING PREVENTIVE MEANS AGAINST ERRORS

Hori Ryoichi; Itoh Kiyoo

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Hori Ryoichi

Hitachi

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Horiguchi Masashi

Hitachi

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Kajigaya Kazuhiko

Hitachi

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Tabei Takashi

Hitachi

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